280 lines
6.8 KiB
Plaintext
280 lines
6.8 KiB
Plaintext
/*
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* Script for GNU linker.
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* Describes layout of sections, location of stack.
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*
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* In this case vectors are at location 0 (reset @ 0x08)
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*
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* +------------+ 0x00400020
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* data |
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* end
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* |(heap) |
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* . .
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* . .
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* |(heap limit)|
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*
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* |- - - - - - |
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* stack bottom 256k
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* +------------+
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*
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* +------------+ 0x0000000
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* |vectors |
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* | |
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* |------------+
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* |text |
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* |data |
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* | | 1024k
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* +------------+
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*/
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#include "../config/sys_config.h"
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/* Split memory into area for vectors and ram */
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MEMORY
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{
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#if(CFG_FLASH_SELECTION_TYPE == FLASH_SELECTION_TYPE_1M)
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flash (rx) : ORIGIN = 0x00000000, LENGTH = 1M
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#else
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flash (rx) : ORIGIN = 0x00000000, LENGTH = 2M
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#endif
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itcm (rwx): ORIGIN = 0x003F0000, LENGTH = 16k
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ram (rw!x): ORIGIN = 0x00400100, LENGTH = 256k - 0x100
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}
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OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
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OUTPUT_ARCH(arm)
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ENTRY(_vector_start);
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_vector_start = ORIGIN(flash);
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SECTIONS
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{
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/* vectors go to vectors region */
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. = ORIGIN(flash);
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.vectors :
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{
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KEEP(*(*.vectors))
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KEEP( *(*.rom1))
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} > flash
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/* instructions go to the text region*/
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. = ORIGIN(itcm);
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.itcm.code ALIGN(8) :
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{
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/* itcm 4KB code */
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*(.text.intc_hdl_entry)
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*(.text.intc_irq)
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*(.text.intc_fiq)
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*(.text.bk_timer_isr)
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*(.text.power_save_wakeup_isr)
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*(.text.bmsg_rx_sender)
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*(.text.bmsg_null_sender)
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*(.text.fclk_get_tick)
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*(.text.flash_read_sr)
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*(.text.flash_write_sr)
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*(.text.flash_clr_qwfr)
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*(.text.set_flash_protect)
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*(.text.flash_read)
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*(.text.flash_read_data)
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*(.text.flash_set_qe)
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*(.text.flash_set_qwfr)
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*(.text.flash_set_line_mode*)
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*(.text.flash_get_line_mode)
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*(.text.flash_write)
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*(.text.flash_ctrl)
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*(.text.power_save_dtim_wake)
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*(.text.sctrl_fix_dpll_div)
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*(.text.flash_get_id)
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*(.text.enter_sleep)
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*(.text.rt_irq_dispatch)
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*(.text.rt_fiq_dispatch)
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*(.text.fclk_hdl)
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*(.text.rt_tick_increase)
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*(.text.rt_thread_yield)
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*(.text.rt_thread_suspend)
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*(.text.platform_is_in_irq_context)
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*(.text.platform_is_in_fiq_context)
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*(.text.platform_is_in_interrupt_context)
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*(.text.portENABLE_IRQ)
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*(.text.portENABLE_FIQ)
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*(.text.portDISABLE_FIQ)
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*(.text.portDISABLE_IRQ)
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*(.text.rt_schedule)
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*(.text.rt_thread_sleep)
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*(.text.rt_exit_critical)
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*(.text.rt_enter_critical)
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*(.text.sctrl_mcu_wakeup)
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*(.text.sctrl_hw_wakeup)
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*(.text.sctrl_cali_dpll)
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*(.text.rt_hw_interrupt_disable)
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*(.text.rt_hw_interrupt_enable)
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*(.text.rt_thread_self)
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*(.text.rt_schedule_remove_thread)
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*(.text.rt_timer_stop)
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*(.text.rt_thread_resume)
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*port_asm.o(.text .text.*)
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*context_gcc.o(.text .text.*)
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*(.text.flash_bypass_op_write)
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*(.text.flash_bypass_op_read)
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} > itcm AT>flash
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_itcmcode_flash_begin = LOADADDR(.itcm.code);
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_itcmcode_ram_begin = ADDR(.itcm.code);
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_itcmcode_ram_end = _itcmcode_ram_begin + SIZEOF(.itcm.code);
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. = ALIGN(0x8);
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/* code, instructions.for example: i=i+1; */
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.text :
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{
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. = ALIGN(4);
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*(.text)
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*(.text.*)
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*(.stub)
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/* .gnu.warning sections are handled specially by elf32.em. */
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*(.gnu.warning)
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*(.gnu.linkonce.t*)
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*(.glue_7t) *(.glue_7)
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KEEP(*(.fini))
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/* section information for finsh shell */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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. = ALIGN(4);
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/* section information for modules */
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. = ALIGN(4);
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__rtmsymtab_start = .;
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KEEP(*(RTMSymTab))
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__rtmsymtab_end = .;
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/* section information for initialization */
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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} > flash
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/* read only data.for example: const int rom_data[3]={1,2,3}; */
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.rodata ALIGN(8) :
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{
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*(.rodata)
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*(.rodata.*)
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*(.gnu.linkonce.r*)
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*(.eh_frame)
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} > flash
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. = ALIGN(4);
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.ctors :
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{
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PROVIDE(__ctors_start__ = .);
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*crtbegin.o(.ctors)
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*crtbegin?.o(.ctors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
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*(SORT(.ctors.*))
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*(.ctors)
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PROVIDE(__ctors_end__ = .);
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}
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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}
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/* The .ARM.exidx section is used for C++ exception handling. */
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/* .ARM.exidx is sorted, so has to go in its own output section. */
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx*)
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*(.gnu.linkonce.armexidx.*)
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} > flash
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__exidx_end = .;
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.dtors :
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{
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PROVIDE(__dtors_start__ = .);
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*crtbegin.o(.dtors)
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*crtbegin?.o(.dtors)
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*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
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*(SORT(.dtors.*))
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*(.dtors)
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PROVIDE(__dtors_end__ = .);
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} > flash
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. = ORIGIN(ram);
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/* globals.for example: int ram_data[3]={4,5,6}; */ /* VMA in RAM, but keep LMA in flash */
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_begin_data = .;
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.data :
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{
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*(.data .data.*)
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*(.sdata)
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. = ALIGN(4);
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/* preinit data */
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PROVIDE_HIDDEN (__preinit_array_start = .);
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KEEP(*(.preinit_array))
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PROVIDE_HIDDEN (__preinit_array_end = .);
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. = ALIGN(4);
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/* init data */
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PROVIDE_HIDDEN (__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array))
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PROVIDE_HIDDEN (__init_array_end = .);
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. = ALIGN(4);
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/* finit data */
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PROVIDE_HIDDEN (__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array))
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PROVIDE_HIDDEN (__fini_array_end = .);
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KEEP(*(.jcr*))
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. = ALIGN(4);
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/* All data end */
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*(.gnu.linkonce.d*)
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SORT(CONSTRUCTORS)
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} >ram AT>flash
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_end_data = .;
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/* Loader will copy data from _flash_begin to _ram_begin..ram_end */
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_data_flash_begin = LOADADDR(.data);
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_data_ram_begin = ADDR(.data);
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_data_ram_end = .;
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/* uninitialized data section - global int i; */
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.bss ALIGN(8):
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{
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_bss_start = .;
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*boot_handlers.o(.bss .bss.* .scommon .sbss .dynbss COMMON)
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*(.bss .bss.*)
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*(.scommon)
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*(.sbss)
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*(.dynbss)
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*(COMMON)
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/* Align here to ensure that the .bss section occupies space up to
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_end. Align after .bss to ensure correct alignment even if the
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.bss section disappears because there are no input sections. */
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. = ALIGN(32 / 8);
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_bss_end = .;
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} > ram
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. = ALIGN (8);
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_empty_ram = .;
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/* This symbol defines end of code/data sections. Heap starts here. */
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PROVIDE(end = .);
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}
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GROUP(
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libgcc.a
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libg.a
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libc.a
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libm.a
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libnosys.a
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)
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