509 lines
14 KiB
C
509 lines
14 KiB
C
// Copyright 2020-2021 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include <soc/soc.h>
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#include "hal_port.h"
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#include "dma_hw.h"
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#include <driver/hal/hal_dma_types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define DMA_LL_REG_OFFSET 0x00010000
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#define DMA_LL_REG_BASE(_dma_unit_id) (SOC_GENER_DMA_REG_BASE+_dma_unit_id*DMA_LL_REG_OFFSET)
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#define CASE_DEV(dev) case DMA_DEV_##dev: return DMA_V_REQ_MUX_##dev
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#define CASE_D() default: return 0
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static inline void dma_ll_init(dma_hw_t *hw)
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{
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int dma_id;
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#if CONFIG_SPE
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hw->prio_mode.v = 0;
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hw->prio_mode.soft_reset = 1; //reset it before anyother operations
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hw->secure_attr.v = 0xFFF;
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hw->privileged_attr.v = 0xFFF;
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#endif
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for (dma_id = 0; dma_id < SOC_DMA_CHAN_NUM_PER_UNIT; dma_id++) {
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hw->config_group[dma_id].ctrl.v = 0;
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hw->config_group[dma_id].dest_start_addr = 0;
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hw->config_group[dma_id].src_start_addr = 0;
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hw->config_group[dma_id].dest_loop_end_addr = 0;
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hw->config_group[dma_id].dest_loop_start_addr = 0;
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hw->config_group[dma_id].src_loop_end_addr = 0;
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hw->config_group[dma_id].src_loop_start_addr = 0;
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hw->config_group[dma_id].req_mux.v = 0;
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hw->config_group[dma_id].src_pause_addr = 0;
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hw->config_group[dma_id].dest_pause_addr = 0;
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hw->config_group[dma_id].status.v = 0;
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}
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}
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static inline uint32_t dma_ll_get_soft_reset_value(dma_hw_t *hw)
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{
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return hw->prio_mode.soft_reset;
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}
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static inline void dma_ll_init_without_channels(dma_hw_t *hw)
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{
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if(0 == dma_ll_get_soft_reset_value(hw)) {
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#if CONFIG_SPE
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hw->prio_mode.v = 0;
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hw->prio_mode.soft_reset = 1; //reset it before anyother operations
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hw->secure_attr.v = 0xFFF;
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hw->privileged_attr.v = 0xFFF;
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#else
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BK_LOGE("DMA", "soft reset is 0, check BAKP!");
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#endif
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}
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}
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static inline uint32_t dma_ll_dev_to_req_mux(uint32 req_mux)
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{
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switch (req_mux) {
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CASE_DEV(DTCM);
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CASE_DEV(UART1);
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CASE_DEV(UART1_RX);
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CASE_DEV(UART2);
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CASE_DEV(UART2_RX);
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CASE_DEV(UART3);
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CASE_DEV(UART3_RX);
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CASE_DEV(GSPI0);
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CASE_DEV(GSPI0_RX);
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CASE_DEV(GSPI1);
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CASE_DEV(GSPI1_RX);
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CASE_DEV(SDIO);
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CASE_DEV(SDIO_RX);
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CASE_DEV(AUDIO);
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CASE_DEV(AUDIO_RX);
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CASE_DEV(I2S);
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CASE_DEV(I2S_CH1);
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CASE_DEV(I2S_CH2);
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CASE_DEV(I2S_RX);
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CASE_DEV(I2S_RX_CH1);
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CASE_DEV(I2S_RX_CH2);
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CASE_DEV(I2S1);
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CASE_DEV(I2S1_RX);
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CASE_DEV(I2S2);
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CASE_DEV(I2S2_RX);
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CASE_DEV(JPEG);
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CASE_DEV(DISP_RX);
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CASE_DEV(SDMADC_RX);
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CASE_DEV(H264);
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CASE_D();
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}
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}
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static inline void dma_ll_enable(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.enable = 1;
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}
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static inline void dma_ll_disable(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.enable = 0;
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}
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static inline uint32_t dma_ll_get_enable_status(dma_hw_t *hw, dma_id_t id)
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{
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return hw->config_group[id].ctrl.enable;
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}
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static inline bool dma_ll_is_id_started(dma_hw_t *hw, dma_id_t id)
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{
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return !!(hw->config_group[id].ctrl.enable == 1);
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}
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static inline void dma_ll_enable_finish_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.finish_int_en = 1;
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}
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static inline void dma_ll_disable_finish_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.finish_int_en = 0;
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}
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static inline void dma_ll_enable_half_finish_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.half_finish_int_en = 1;
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}
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static inline void dma_ll_disable_half_finish_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.half_finish_int_en = 0;
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}
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static inline void dma_ll_enable_bus_err_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].req_mux.bus_err_int_en = 1;
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}
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static inline void dma_ll_disable_bus_err_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].req_mux.bus_err_int_en = 0;
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}
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static inline void dma_ll_enable_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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dma_ll_enable_half_finish_interrupt(hw, id);
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dma_ll_enable_finish_interrupt(hw, id);
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dma_ll_enable_bus_err_interrupt(hw,id);
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}
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static inline void dma_ll_disable_interrupt(dma_hw_t *hw, dma_id_t id)
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{
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dma_ll_disable_half_finish_interrupt(hw, id);
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dma_ll_disable_finish_interrupt(hw, id);
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dma_ll_disable_bus_err_interrupt(hw,id);
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}
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static inline void dma_ll_clear_finish_interrupt_status(dma_hw_t *hw, dma_id_t id)
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{
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/*other interrupt bit also wirte 1 to clear, so should not effect other bits*/
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hw->config_group[id].status.v = BIT(DMA_FINISH_INT_POS);
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}
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static inline void dma_ll_clear_half_finish_interrupt_status(dma_hw_t *hw, dma_id_t id)
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{
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/*other interrupt bit also wirte 1 to clear, so should not effect other bits*/
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hw->config_group[id].status.v = BIT(DMA_HALF_FINISH_INT_POS);
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}
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static inline void dma_ll_clear_bus_err_interrupt_status(dma_hw_t *hw, dma_id_t id)
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{
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/*other interrupt bit also wirte 1 to clear, so should not effect other bits*/
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hw->config_group[id].status.v = BIT(DMA_BUS_ERR_INT_POS);
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}
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static inline void dma_ll_clear_interrupt_status(dma_hw_t *hw, dma_id_t id)
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{
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dma_ll_clear_half_finish_interrupt_status(hw, id);
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dma_ll_clear_finish_interrupt_status(hw, id);
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dma_ll_clear_bus_err_interrupt_status(hw, id);
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}
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static inline uint32_t dma_ll_repeat_wr_pause(dma_hw_t *hw, dma_id_t id)
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{
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return (uint32_t)(hw->config_group[id].status.repeat_wr_pause);
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}
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static inline uint32_t dma_ll_repeat_rd_pause(dma_hw_t *hw, dma_id_t id)
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{
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return (uint32_t)(hw->config_group[id].status.repeat_rd_pause);
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}
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static inline uint32_t dma_ll_finish_interrupt_cnt(dma_hw_t *hw, dma_id_t id)
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{
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return (uint32_t)(hw->config_group[id].status.finish_int_counter);
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}
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static inline uint32_t dma_ll_half_finish_interrupt_cnt(dma_hw_t *hw, dma_id_t id)
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{
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return (uint32_t)(hw->config_group[id].status.half_finish_int_counter);
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}
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static inline bool dma_ll_is_finish_interrupt_triggered(dma_hw_t *hw, dma_id_t id)
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{
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return !!(hw->config_group[id].status.finish_int & 0x1);
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}
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static inline bool dma_ll_is_half_finish_interrupt_triggered(dma_hw_t *hw, dma_id_t id)
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{
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return !!(hw->config_group[id].status.half_finish_int & 0x1);
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}
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static inline bool dma_ll_is_bus_err_interrupt_triggered(dma_hw_t *hw, dma_id_t id)
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{
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return !!(hw->config_group[id].status.bus_err_int & 0x1);
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}
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static inline void dma_ll_reset_config_to_default(dma_hw_t *hw, volatile dma_id_t id)
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{
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hw->config_group[id].ctrl.v = 0;
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hw->config_group[id].dest_start_addr = 0;
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hw->config_group[id].src_start_addr = 0;
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hw->config_group[id].dest_loop_end_addr = 0;
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hw->config_group[id].dest_loop_start_addr = 0;
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hw->config_group[id].src_loop_end_addr = 0;
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hw->config_group[id].src_loop_start_addr = 0;
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hw->config_group[id].req_mux.v = 0;
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hw->config_group[id].src_pause_addr = 0;
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hw->config_group[id].dest_pause_addr = 0;
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}
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static inline void dma_ll_set_work_mode(dma_hw_t *hw, dma_id_t id, uint32_t mode)
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{
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hw->config_group[id].ctrl.mode = mode & 0x01;
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}
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#define dma_ll_set_mode_single(hw, id) dma_ll_set_work_mode(hw, id, DMA_V_WORK_MODE_SINGLE)
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#define dma_ll_set_mode_repeat(hw, id) dma_ll_set_work_mode(hw, id, DMA_V_WORK_MODE_REPEAT)
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static uint32_t dma_ll_get_work_mode(dma_hw_t *hw, dma_id_t id)
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{
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return hw->config_group[id].ctrl.mode;
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}
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static inline void dma_ll_set_chan_prio(dma_hw_t *hw, dma_id_t id, uint32_t chan_prio)
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{
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hw->config_group[id].ctrl.chan_prio = chan_prio & 0x07;
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}
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static inline void dma_ll_set_dest_data_width(dma_hw_t *hw, dma_id_t id, uint32_t data_width)
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{
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hw->config_group[id].ctrl.dest_data_width = data_width & 0x03;
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}
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static inline void dma_ll_set_src_data_width(dma_hw_t *hw, dma_id_t id, uint32_t data_width)
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{
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hw->config_group[id].ctrl.src_data_width = data_width & 0x03;
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}
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static inline void dma_ll_set_dest_req_mux(dma_hw_t *hw, dma_id_t id, uint32_t req_mux)
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{
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hw->config_group[id].req_mux.dest_req_mux = (dma_ll_dev_to_req_mux(req_mux)) & 0x1f;
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}
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static inline void dma_ll_set_src_req_mux(dma_hw_t *hw, dma_id_t id, uint32_t req_mux)
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{
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hw->config_group[id].req_mux.src_req_mux = (dma_ll_dev_to_req_mux(req_mux)) & 0x1f;
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}
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static inline void dma_ll_set_pixel_trans_type(dma_hw_t *hw, dma_id_t id, uint32_t type)
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{
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hw->config_group[id].req_mux.pixel_trans_type = (type & 0x3);
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}
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static inline uint32_t dma_ll_get_pixel_trans_type(dma_hw_t *hw, dma_id_t id)
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{
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return (hw->config_group[id].req_mux.pixel_trans_type & 0x3);
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}
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static inline void dma_ll_enable_src_addr_inc(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.src_addr_inc_en = 1;
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}
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static inline void dma_ll_disable_src_addr_inc(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.src_addr_inc_en = 0;
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}
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static inline void dma_ll_enable_dest_addr_inc(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.dest_addr_inc_en = 1;
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}
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static inline void dma_ll_disable_dest_addr_inc(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.dest_addr_inc_en = 0;
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}
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static inline void dma_ll_enable_src_addr_loop(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.src_addr_loop_en = 1;
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}
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static inline void dma_ll_disable_src_addr_loop(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.src_addr_loop_en = 0;
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}
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static inline void dma_ll_enable_dest_addr_loop(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.dest_addr_loop_en = 1;
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}
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static inline void dma_ll_disable_dest_addr_loop(dma_hw_t *hw, dma_id_t id)
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{
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hw->config_group[id].ctrl.dest_addr_loop_en = 0;
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}
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static inline void dma_ll_set_dest_start_addr(dma_hw_t *hw, volatile dma_id_t id, uint32_t addr)
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{
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hw->config_group[id].dest_start_addr = addr;
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}
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static inline void dma_ll_set_src_start_addr(dma_hw_t *hw, dma_id_t id, uint32_t addr)
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{
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hw->config_group[id].src_start_addr = addr;
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}
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static inline void dma_ll_set_dest_loop_addr(dma_hw_t *hw, dma_id_t id, uint32_t start_addr, uint32_t end_addr)
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{
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hw->config_group[id].dest_loop_start_addr = start_addr;
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hw->config_group[id].dest_loop_end_addr = end_addr;
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}
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static inline void dma_ll_set_src_loop_addr(dma_hw_t *hw, dma_id_t id, uint32_t start_addr, uint32_t end_addr)
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{
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hw->config_group[id].src_loop_start_addr = start_addr;
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hw->config_group[id].src_loop_end_addr = end_addr;
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}
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#define DMA_LL_TRANS_LEN_MAX (0x10000)
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static inline uint32_t dma_ll_get_transfer_len_max(dma_hw_t *hw)
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{
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return DMA_LL_TRANS_LEN_MAX;
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}
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static inline void dma_ll_set_transfer_len(dma_hw_t *hw, dma_id_t id, uint32_t tran_len)
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{
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hw->config_group[id].ctrl.transfer_len = (tran_len - 1) & 0xffff;
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}
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static inline uint32_t dma_ll_get_remain_len(dma_hw_t *hw, dma_id_t id)
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{
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return (uint32_t)hw->config_group[id].status.remain_len;
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}
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static inline void dma_ll_set_prio_mode(dma_hw_t *hw, uint32_t prio_mode)
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{
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#if CONFIG_SPE
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hw->prio_mode.prio_mode = prio_mode & 0x1;
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#endif
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}
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#define dma_ll_set_prio_mode_round_robin(hw) dma_ll_set_prio_mode(hw, DMA_V_PRIO_MODE_ROUND_ROBIN)
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#define dma_ll_set_prio_mode_fixed_prio(hw) dma_ll_set_prio_mode(hw, DMA_V_PRIO_MODE_FIXED_PRIO)
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#if CONFIG_SPE
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static inline void dma_ll_set_secure_attr(dma_hw_t *hw, dma_id_t id, dma_sec_attr_t attr)
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{
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if (attr == DMA_ATTR_NON_SEC) {
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hw->secure_attr.attr &= ~(BIT(id) & 0xFFF);
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} else if (attr == DMA_ATTR_SEC) {
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hw->secure_attr.attr |= (BIT(id) & 0xFFF);
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}
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}
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static inline void dma_ll_set_privileged_attr(dma_hw_t *hw, dma_id_t id, dma_sec_attr_t attr)
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{
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if (attr == DMA_ATTR_NON_SEC) {
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hw->privileged_attr.attr &= ~(BIT(id) & 0xFFF);
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} else if (attr == DMA_ATTR_SEC) {
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hw->privileged_attr.attr |= (BIT(id) & 0xFFF);
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}
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}
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static inline void dma_ll_set_int_allocate(dma_hw_t *hw, dma_id_t id,dma_int_id_t int_id)
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{
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hw->int_allocate.status |= (int_id)<<BIT(id);
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//os_printf("%s and %x\r\n",__func__,hw->int_allocate.v);
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}
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#endif
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static inline void dma_ll_set_src_pause_addr(dma_hw_t *hw, dma_id_t id, uint32_t addr)
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{
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hw->config_group[id].src_pause_addr = addr;
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}
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static inline void dma_ll_set_dest_pause_addr(dma_hw_t *hw, dma_id_t id, uint32_t addr)
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{
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hw->config_group[id].dest_pause_addr = addr;
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}
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static inline uint32_t dma_ll_get_src_read_addr(dma_hw_t *hw, dma_id_t id)
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{
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return hw->config_group[id].src_rd_addr;
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}
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static inline uint32_t dma_ll_get_dest_write_addr(dma_hw_t *hw, dma_id_t id)
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|
{
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return hw->config_group[id].dest_wr_addr;
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}
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|
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static inline void dma_ll_set_dest_burst_len(dma_hw_t *hw, dma_id_t id, uint32_t len)
|
|
{
|
|
hw->config_group[id].req_mux.dtst_burst_len = (len & 0x3);
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}
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|
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|
static inline uint32_t dma_ll_get_dest_burst_len(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
return (hw->config_group[id].req_mux.dtst_burst_len & 0x3);
|
|
}
|
|
|
|
static inline void dma_ll_set_src_burst_len(dma_hw_t *hw, dma_id_t id, uint32_t len)
|
|
{
|
|
hw->config_group[id].req_mux.src_burst_len = (len & 0x3);
|
|
}
|
|
|
|
static inline uint32_t dma_ll_get_src_burst_len(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
return (hw->config_group[id].req_mux.src_burst_len & 0x3);
|
|
}
|
|
|
|
static inline void dma_ll_bus_err_int_enable(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
hw->config_group[id].req_mux.bus_err_int_en = 0x1;
|
|
}
|
|
|
|
static inline void dma_ll_bus_err_int_disable(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
hw->config_group[id].req_mux.bus_err_int_en = 0x0;
|
|
}
|
|
|
|
static inline void dma_ll_set_dest_sec_attr(dma_hw_t *hw, dma_id_t id, uint32_t attr)
|
|
{
|
|
hw->config_group[id].req_mux.dest_sec_attr = attr & 0x1;
|
|
}
|
|
|
|
static inline void dma_ll_set_src_sec_attr(dma_hw_t *hw, dma_id_t id, uint32_t attr)
|
|
{
|
|
hw->config_group[id].req_mux.src_sec_attr = attr & 0x1;
|
|
}
|
|
|
|
|
|
static inline void dma_ll_set_src_read_interval(dma_hw_t *hw, dma_id_t id, uint32_t interval)
|
|
{
|
|
hw->config_group[id].req_mux.src_read_interval = interval & 0xf;
|
|
}
|
|
|
|
static inline uint32_t dma_ll_get_src_read_interval(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
return (hw->config_group[id].req_mux.src_read_interval & 0xf);
|
|
}
|
|
|
|
static inline void dma_ll_set_dest_write_interval(dma_hw_t *hw, dma_id_t id, uint32_t interval)
|
|
{
|
|
hw->config_group[id].req_mux.dest_write_interval = interval & 0xf;
|
|
}
|
|
|
|
static inline uint32_t dma_ll_get_dest_write_interval(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
return (hw->config_group[id].req_mux.dest_write_interval & 0xf);
|
|
}
|
|
|
|
|
|
static inline void dma_ll_flush_src_buffer(dma_hw_t *hw, dma_id_t id)
|
|
{
|
|
hw->config_group[id].status.flush_src_buff = 1;
|
|
BK_WHILE(hw->config_group[id].status.flush_src_buff);
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|