176 lines
2.5 KiB
ArmAsm
Executable File
176 lines
2.5 KiB
ArmAsm
Executable File
/*
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* Copyright (c) 2021-2022 Beken Corporation
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* All rights reserved.
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*
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*/
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#include "core_v5.h"
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#define MTIMER (0xE6000000)
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#define MTIMERCMP (0xE6000008)
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.global arch_int_disable
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.global arch_int_enable
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.global arch_int_restore
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.global arch_int_disabled
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.global arch_fence
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.global arch_atomic_clear
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.global arch_atomic_set
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.global riscv_get_mtimercmp
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.global riscv_get_mtimer
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.global riscv_set_mtimercmp
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.global riscv_get_cycle
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.global riscv_get_instruct_cnt
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.global arch_get_int_status
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.global riscv_sys_call1
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.global riscv_sys_call2
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.global riscv_sys_call3
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.global riscv_sys_call4
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//.section .text
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.section .itcm_sec_code, "ax"
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/*
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* u32 arch_get_int_status(void);
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*/
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arch_get_int_status:
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csrr a0, uip // return value
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csrr t0, uie
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and a0, a0, t0
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ret
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/*
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* u32 arch_int_disable(void);
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*/
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arch_int_disable:
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csrrci a0, ustatus, USTATUS_UIE
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ret
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/*
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* void arch_int_enable(void);
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*/
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arch_int_enable:
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csrsi ustatus, USTATUS_UIE
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ret
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/*
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* void arch_int_restore(u32 int_flag);
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*/
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arch_int_restore:
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csrw ustatus, a0
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ret
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/*
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* u32 arch_int_disabled(void);
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*/
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arch_int_disabled:
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csrr a0, ustatus
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c.andi a0, USTATUS_UIE
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xori a0, a0, USTATUS_UIE
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ret
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#if 1
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/*
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* void arch_fence(void);
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*/
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arch_fence:
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// fence iorw, iorw
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ret
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/*
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* void arch_atomic_clear(u32 * lock_addr);
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*/
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arch_atomic_clear:
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amoswap.w.rl x0, x0, (a0)
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ret
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/*
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* void arch_atomic_set(u32 * lock_addr);
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*/
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arch_atomic_set:
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addi t0, x0, 1
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swap_again:
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amoswap.w.aq t0, t0, (a0)
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bnez t0, swap_again
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ret
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#endif
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/*
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* u64 riscv_get_mtimercmp(void);
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*/
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riscv_get_mtimercmp:
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li t0, MTIMERCMP
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lw a0, 0(t0)
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lw a1, 4(t0)
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ret
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/*
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* u64 riscv_get_mtimer(void);
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*/
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riscv_get_mtimer:
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li t0, MTIMER
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read_mtimer:
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lw a1, 4(t0)
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lw a0, 0(t0)
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lw t1, 4(t0)
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bne a1, t1, read_mtimer
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ret
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/*
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* void riscv_set_mtimercmp(u64 new_time);
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*/
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riscv_set_mtimercmp:
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li t0, MTIMERCMP
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li t1, -1
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sw t1, 4(t0)
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fence
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sw a0, 0(t0)
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sw a1, 4(t0)
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ret
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/*
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* u64 riscv_get_cycle(void);
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*/
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riscv_get_cycle:
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read_cycle_again:
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rdcycleh a1
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rdcycle a0
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rdcycleh t0
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bne a1, t0, read_cycle_again
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ret
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/*
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* u64 riscv_get_instruct_cnt(void);
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*/
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riscv_get_instruct_cnt:
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read_instr_again:
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rdinstreth a1
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rdinstret a0
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rdinstreth t0
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bne a1, t0, read_instr_again
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ret
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/*
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* u32 riscv_sys_call(u32 id, ....);
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*/
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riscv_sys_call1:
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ecall
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ret
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riscv_sys_call2:
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ecall
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ret
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riscv_sys_call3:
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ecall
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ret
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riscv_sys_call4:
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ecall
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ret
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