237 lines
8.0 KiB
C
Executable File
237 lines
8.0 KiB
C
Executable File
#include <stdio.h>
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#include "platform.h"
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#include <os/os.h>
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#include <components/system.h>
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#include "cache.h"
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#include "mon_call.h"
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/* CSR NDS_ICM_CFG */
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#define ISET_MSK ((1ULL << 2) | (1ULL << 1) | (1ULL << 0))
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#define IWAY_MSK ((1ULL << 5) | (1ULL << 4) | (1ULL << 3))
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#define ISIZE_MSK ((1ULL << 8) | (1ULL << 7) | (1ULL << 6))
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/* CSR NDS_DCM_CFG */
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#define DSET_MSK ((1ULL << 2) | (1ULL << 1) | (1ULL << 0))
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#define DWAY_MSK ((1ULL << 5) | (1ULL << 4) | (1ULL << 3))
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#define DSIZE_MSK ((1ULL << 8) | (1ULL << 7) | (1ULL << 6))
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/* CSR NDS_MCACHE_CTL */
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#define DC_WARND_MSK (3UL << 13)
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#define CCTL_SUEN_MSK (1ULL << 8)
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/* CSR NDS_MMSC_CFG */
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#define CCTLCSR_MSK (1ULL << 16)
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#define VCCTL_MSK ((1ULL << 18) | (1ULL << 19))
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/* AndeStar CCTL Command Machine mode */
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/* Allow S/U mode */
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#define CCTL_L1D_VA_INVAL 0
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/* Allow S/U mode */
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#define CCTL_L1D_VA_WB 1
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/* Allow S/U mode */
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#define CCTL_L1D_VA_WBINVAL 2
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#define CCTL_L1D_VA_LOCK 3
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#define CCTL_L1D_VA_UNLOCK 4
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#define CCTL_L1D_WBINVAL_ALL 6
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#define CCTL_L1D_WB_ALL 7
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/* Allow S/U mode */
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#define CCTL_L1I_VA_INVAL 8
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#define CCTL_L1I_VA_LOCK 11
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#define CCTL_L1I_VA_UNLOCK 12
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#define CCTL_L1D_IX_INVAL 16
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#define CCTL_L1D_IX_WB 17
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#define CCTL_L1D_IX_WBINVAL 18
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#define CCTL_L1D_IX_RTAG 19
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#define CCTL_L1D_IX_RDATA 20
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#define CCTL_L1D_IX_WTAG 21
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#define CCTL_L1D_IX_WDATA 22
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#define CCTL_L1D_INVAL_ALL 23
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#define CCTL_L1I_IX_INVAL 24
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#define CCTL_L1I_IX_RTAG 27
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#define CCTL_L1I_IX_RDATA 28
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#define CCTL_L1I_IX_WTAG 29
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#define CCTL_L1I_IX_WDATA 30
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#define USE_CCTL 0
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#define BUF_SIZE 0x100
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/* SMU.SYSTEMCFG Configuration Register */
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#define L2C_CTL_OFF 8
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#define L2C_CTL_MSK (0x1 << L2C_CTL_OFF)
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/* Configuration Register */
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#define L2C_SIZE_OFF 7
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#define L2C_SIZE_MSK (0x1F << L2C_SIZE_OFF)
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#define L2C_SIZE_0KB (0x00 << L2C_SIZE_OFF)
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#define L2C_SIZE_128KB (0x01 << L2C_SIZE_OFF)
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#define L2C_SIZE_256KB (0x02 << L2C_SIZE_OFF)
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#define L2C_SIZE_512KB (0x04 << L2C_SIZE_OFF)
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#define L2C_SIZE_1024KB (0x08 << L2C_SIZE_OFF)
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#define L2C_SIZE_2048KB (0x10 << L2C_SIZE_OFF)
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#define L2C_LINE_SIZE 32
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/* Control Register */
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#define L2C_ENABLE 0x1
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/* Prefetch Threshold */
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#define PFTHRES_OFF 1
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#define PFTHRES_MSK (0x3 << PFTHRES_OFF)
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/* Instruction Prefetch Depth */
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#define IPFDPT_OFF 3
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#define IPFDPT_MSK (0x3 << IPFDPT_OFF)
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#define IPFDPT_3REQ (0x3 << IPFDPT_OFF)
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/* Data Prefetch Depth */
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#define DPFDPT_OFF 5
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#define DPFDPT_MSK (0x3 << DPFDPT_OFF)
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#define DPFDPT_3REQ (0x3 << DPFDPT_OFF)
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/* Tag Ram output cycle */
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#define TRAMOCTL_OFF 8
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#define TRAMOCTL_MSK (0x3 << TRAMOCTL_OFF)
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/* Tag Ram setup cycle */
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#define TRAMICTL_OFF 10
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#define TRAMICTL_MSK (0x1 << TRAMICTL_OFF)
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/* Data Ram output cycle */
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#define DRAMOCTL_OFF 11
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#define DRAMOCTL_MSK (0x3 << DRAMOCTL_OFF)
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/* Data Ram setup cycle */
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#define DRAMICTL_OFF 13
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#define DRAMICTL_MSK (0x1 << DRAMICTL_OFF)
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/* CCTL Command Register */
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#define CCTL_L2_IX_INVAL 0x0
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#define CCTL_L2_IX_WB 0x1
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#define CCTL_L2_IX_WBINVAL 0x2
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#define CCTL_L2_PA_INVAL 0x8
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#define CCTL_L2_PA_WB 0x9
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#define CCTL_L2_PA_WBINVAL 0xA
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#define CCTL_L2_TGT_WRITE 0x10
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#define CCTL_L2_TGT_READ 0x11
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#define CCTL_L2_WBINVAL_ALL 0x12
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/* CCTL Access Line Registers */
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#define CCTL_L2_ACC_SET_OFF 5
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#define CCTL_L2_ACC_SET_MSK (0x7FFF << CCTL_L2_ACC_SET_OFF)
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#define CCTL_L2_ACC_WAY_OFF 28
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#define CCTL_L2_ACC_WAY_MSK (0xF << CCTL_L2_ACC_WAY_OFF)
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#define CCTL_L2_ACC_RAMID_OFF 26
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#define CCTL_L2_ACC_RAMID_MSK (0x3 << CCTL_L2_ACC_RAMID_OFF)
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/* CCTL Status Register */
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#define CCTL_L2_ST_IDLE 0
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#define CCTL_L2_ST_RUNNING 1
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#define CCTL_L2_ST_INVALID 2
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#define CCTL_ST_MASK 0xF
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#define SRAM_CACHE_CONFIG_BASE 0x3fff0048
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#if !CONFIG_CACHE_CUSTOM_SRAM_MAPPING
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#if !CONFIG_CACHE_ENABLE
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const unsigned int g_sram_addr_map[SRAM_BLOCK_COUNT] = {
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0x30060000,
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0x30020000,
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0x30040000,
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0x30000000
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};
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#else //#if CONFIG_CACHE_ENABLE
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const unsigned int g_sram_addr_map[SRAM_BLOCK_COUNT] = {
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0x38000000,
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0x30020000,
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0x38020000,
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0x30000000
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};
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#endif //#if CONFIG_CACHE_ENABLE
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#else //#if !CONFIG_CACHE_CUSTOM_SRAM_MAPPING
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extern unsigned int g_sram_addr_map[SRAM_BLOCK_COUNT];
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#endif //#if !CONFIG_CACHE_CUSTOM_SRAM_MAPPING
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void sram_dcache_map(void)
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{
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int i = 0;
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unsigned int addr, data;
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for(i = 0; i < SRAM_BLOCK_COUNT; i++)
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{
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addr = SRAM_CACHE_CONFIG_BASE + (i * sizeof(data));
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data = *((volatile unsigned int *) (addr));
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*((volatile unsigned int *) (addr)) = (g_sram_addr_map[i]) + (data & 0x03ff);
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}
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}
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int show_cache_config_info(void)
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{
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return 1;
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}
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void flush_dcache(void *va, long size)
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{
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unsigned int tmp = 0, line_size = 32;
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unsigned int start_line_va, end_line_va;
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start_line_va = (((unsigned int)va) & (~(line_size - 1)));
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end_line_va = ((((unsigned int)va) + size + line_size - 1) & (~(line_size - 1)));
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// flush area: [start_line_va, end_line_va) .
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size = end_line_va - start_line_va;
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/* L1C DCache write back and invalidate */
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while (tmp < size)
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{
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/* Write back and invalid one cache line each time */
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write_csr(NDS_UCCTLBEGINADDR, (unsigned long)(start_line_va + tmp));
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tmp += line_size;
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write_csr(NDS_UCCTLCOMMAND, CCTL_L1D_VA_WBINVAL);
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}
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}
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void flush_all_dcache(void)
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{
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int i = 0;
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for(i = 0; i < SRAM_BLOCK_COUNT; i++)
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{
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if(g_sram_addr_map[i] & 0x08000000)
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{
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mon_flush_dcache(g_sram_addr_map[i]);
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return;
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}
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}
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}
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void enable_dcache(int enable)
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{
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// RISC-V enable dcache as default
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return;
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}
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void flush_icache(void *va, long size)
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{
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unsigned int line_size = 32;
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unsigned int start_line_va, end_va;
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start_line_va = (((unsigned int)va) & (~(line_size - 1)));
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end_va = (unsigned int)va + size;
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// flush area: [start_line_va, end_va) .
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/* L1C iCache write back and invalidate */
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while (start_line_va < end_va)
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{
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/* Write back and invalid one cache line each time */
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write_csr(NDS_UCCTLBEGINADDR, (unsigned long)start_line_va);
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start_line_va += line_size;
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write_csr(NDS_UCCTLCOMMAND, CCTL_L1I_VA_INVAL);
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}
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}
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void flush_all_icache(void)
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{
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__asm volatile( "fence.i" );
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}
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