235 lines
6.4 KiB
C
235 lines
6.4 KiB
C
// Copyright 2020-2021 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "icu_hal.h"
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#include "clock_driver.h"
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#include "power_hal.h"
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#include "spi_hal.h"
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#include "spi_ll.h"
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#include <driver/hal/hal_spi_types.h>
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#include "sys_hal.h"
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#include "bk_misc.h"
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#define CONFIG_SPI_MAX_BAUD_RATE 49000000 //49M
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#if (!CONFIG_SYSTEM_CTRL)
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/* spi_clk(more than 1M) support list when source_clk = XTAL_26M
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* sort the numbers from largest to smallest, otherwize binary_search will not work
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*/
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static const uint32_t s_spi_clk_list[] = {
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26000000, /**< DIV1 */
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13000000, /**< DIV2 */
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6500000, /**< DIV4 */
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5200000, /**< DIV5 */
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3250000, /**< DIV8 */
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2600000, /**< DIV10 */
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2000000, /**< DIV13 */
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1625000, /**< DIV16 */
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1300000, /**< DIV20 */
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1040000, /**< DIV25 */
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1000000, /**< DIV26 */
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};
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static int binary_search(const uint32_t *array, uint32_t size, uint32_t target)
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{
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uint32_t left = 0;
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uint32_t right = size - 1;
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uint32_t mid = (left + right) / 2;
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while (left <= right && mid < size) {
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mid = (left + right) / 2;
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if (array[mid] == target) {
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return mid;
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}
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if (target > array[mid]) {
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right = mid - 1;
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} else {
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left = mid + 1;
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}
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}
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return BK_FAIL;
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}
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#endif
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bk_err_t spi_hal_init(spi_hal_t *hal)
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{
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spi_ll_init(hal->hw);
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return BK_OK;
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}
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/* 1. bit_width, clk_rate, cpol, cpha, master/slave, 4line, int_level=0, rxovf_en=1, txudf_en=1
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* 2. if 4 wire mode, enable sla_release_int_en, clear slv_release_int
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* 3. set rx_callback, tx_need_write_callback, tx_finish_callback
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* 4. enable spi, bit[23] spi_en
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* 5. if need clk_rate more than 26M, need close i2s to avoid conflict about APLL 98M clock
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*/
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bk_err_t spi_hal_configure(spi_hal_t *hal, const spi_config_t *config)
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{
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spi_ll_enable_tx_underflow_int(hal->hw);
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spi_ll_enable_rx_overflow_int(hal->hw);
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spi_ll_disable_tx_fifo_int(hal->hw);
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spi_ll_enable_rx_fifo_int(hal->hw);
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spi_hal_set_baud_rate(hal, config->baud_rate);
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#if (CONFIG_SPI_BYTE_INTERVAL)
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spi_hal_set_byte_interval(hal, config->byte_interval);
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#endif
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spi_ll_set_bit_width(hal->hw, config->bit_width);
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spi_ll_set_first_bit(hal->hw, config->bit_order);
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spi_ll_set_cpol(hal->hw, config->polarity);
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spi_ll_set_cpha(hal->hw, config->phase);
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if (config->role == SPI_ROLE_SLAVE) {
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spi_ll_set_role_slave(hal->hw);
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} else {
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spi_ll_set_role_master(hal->hw);
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}
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spi_ll_set_wire_mode(hal->hw, config->wire_mode);
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if (config->wire_mode == SPI_4WIRE_MODE) {
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spi_ll_enable_slave_release_int(hal->hw);
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} else {
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spi_ll_disable_slave_release_int(hal->hw);
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}
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spi_ll_enable_tx_finish_int(hal->hw);
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spi_ll_enable_rx_finish_int(hal->hw);
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spi_ll_clear_int_status(hal->hw);
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return BK_OK;
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}
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bk_err_t spi_hal_start_common(spi_hal_t *hal)
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{
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spi_ll_enable(hal->hw);
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return BK_OK;
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}
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bk_err_t spi_hal_stop_common(spi_hal_t *hal)
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{
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spi_ll_disable(hal->hw);
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return BK_OK;
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}
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/* 1) src_clk=dco, div = ((dco_clk/2) / spi_clk) - 1
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* 2) src_clk=xtal_26M, div = xtal_26m / spi_clk - 1
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*/
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bk_err_t spi_hal_set_baud_rate(spi_hal_t *hal, uint32_t baud_rate)
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{
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uint32_t src_clk = 0;
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uint32_t spi_clk = baud_rate;
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uint32_t clk_div = 0;
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if (baud_rate > CONFIG_SPI_MAX_BAUD_RATE) {
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HAL_LOGW("baud_rate(%d) not support, spi support max baud_rate:%d\r\n", baud_rate, CONFIG_SPI_MAX_BAUD_RATE);
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spi_clk = CONFIG_SPI_MAX_BAUD_RATE;
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}
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#if (CONFIG_SYSTEM_CTRL)
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if (baud_rate <= CONFIG_XTAL_FREQ) {
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#else
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if (binary_search(s_spi_clk_list, ARRAY_SIZE(s_spi_clk_list), baud_rate) >= 0) {
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#endif
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HAL_LOGI("spi select src_clk xtal\r\n");
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src_clk = CONFIG_XTAL_FREQ;
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#if (CONFIG_SYSTEM_CTRL)
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sys_hal_spi_select_clock(hal->id, SPI_CLK_XTAL);
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clk_div = (src_clk / (2 * spi_clk)) & SPI_F_CLK_DIV_M;
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#else
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clk_set_spi_clk_26m(hal->id);
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clk_div = (src_clk / spi_clk - 1) & SPI_F_CLK_DIV_M;
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#endif
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} else {
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#if (CONFIG_SYSTEM_CTRL)
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HAL_LOGI("spi select src_clk apll\r\n");
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#if CONFIG_SOC_BK7256XX
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//enable apll clock and set clock config
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sys_hal_apll_en(true);
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sys_hal_cb_manu_val_set(SPI_EN_APLL_MANU_VAL);
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sys_hal_ana_reg11_vsel_set(SPI_EN_APLL_VSEL_VAL);
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src_clk = SPI_APLL_98M;
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#else
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sys_hal_apll_en(1);
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//set apll clock config
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sys_hal_apll_cal_val_set(0x8973CA6F);
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sys_hal_apll_config_set(0xC2A0AE86);
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sys_hal_apll_spi_trigger_set(1);
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delay(10);
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sys_hal_apll_spi_trigger_set(0);
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src_clk = SPI_APLL_98M;
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#endif
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sys_hal_spi_select_clock(hal->id, SPI_CLK_APLL);
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clk_div = (src_clk / (2 * spi_clk)) & SPI_F_CLK_DIV_M;
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#else
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HAL_LOGI("spi select src_clk dco\r\n");
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src_clk = CONFIG_DCO_FREQ >> 1; /* The spi clock is derived from the dco clock divided by 2 */
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clk_set_spi_clk_dco(hal->id);
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clk_div = (src_clk / spi_clk) & SPI_F_CLK_DIV_M;
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#endif
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}
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HAL_LOGD("baud_rate = %d, src_clk = %d, clk_div = 0x%x.\r\n", baud_rate, src_clk, clk_div);
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spi_ll_set_clk_div(hal->hw, clk_div);
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return BK_OK;
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}
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bk_err_t spi_hal_read_byte(spi_hal_t *hal, uint8_t *data)
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{
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if (spi_ll_is_rx_fifo_rd_ready(hal->hw)) {
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*data = spi_ll_read_byte(hal->hw);
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return BK_OK;
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}
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return BK_ERR_SPI_FIFO_RD_NOT_READY;
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}
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bk_err_t spi_hal_enable_tx_rx(spi_hal_t *hal)
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{
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spi_ll_enable_tx_rx(hal->hw);
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return BK_OK;
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}
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bk_err_t spi_hal_duplex_config(spi_hal_t *hal)
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{
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spi_ll_disable_tx_underflow_int(hal->hw);
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spi_ll_disable_rx_overflow_int(hal->hw);
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spi_ll_disable_tx_fifo_int(hal->hw);
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spi_ll_disable_rx_fifo_int(hal->hw);
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spi_ll_enable_slave_release_int(hal->hw);
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spi_ll_disable_tx(hal->hw);
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spi_ll_disable_rx(hal->hw);
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spi_ll_enable_tx_finish_int(hal->hw);
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spi_ll_enable_rx_finish_int(hal->hw);
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spi_ll_clear_int_status(hal->hw);
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return BK_OK;
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}
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bk_err_t spi_hal_duplex_release(spi_hal_t *hal)
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{
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spi_ll_enable_tx_underflow_int(hal->hw);
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spi_ll_enable_rx_overflow_int(hal->hw);
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spi_ll_disable_tx_fifo_int(hal->hw);
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spi_ll_enable_rx_fifo_int(hal->hw);
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spi_ll_disable_tx(hal->hw);
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return BK_OK;
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}
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#if (CONFIG_SPI_PM_CB_SUPPORT)
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void spi_hal_backup(spi_hal_t *hal, uint32_t *pm_backup)
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{
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spi_ll_backup(hal->hw, pm_backup);
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}
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void spi_hal_restore(spi_hal_t *hal, uint32_t *pm_backup)
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{
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spi_ll_restore(hal->hw, pm_backup);
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}
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#endif
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