529 lines
14 KiB
C
529 lines
14 KiB
C
#include <common/bk_include.h>
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#include "bk_arm_arch.h"
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#if CONFIG_SDCARD
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#include "sdio_driver.h"
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#include "bk_drv_model.h"
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#include "bk_sys_ctrl.h"
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#include <os/mem.h>
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#include "bk_icu.h"
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#include "bk_gpio.h"
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#include <os/os.h>
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#include "gpio_driver.h"
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#include <driver/hal/hal_gpio_types.h>
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#if CONFIG_SOC_BK7256XX
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#include "sys_types.h"
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#include "sys_driver.h"
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#include <driver/gpio.h>
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#endif
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/******************************************************************************/
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/**************************** platform function *******************************/
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/******************************************************************************/
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/******************************************************************************/
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/**************************** interface function ******************************/
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/******************************************************************************/
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#if (CONFIG_SOC_BK7256XX)
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/* clk_index: includes clock src and clock divider info */
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void sdio_set_clock(UINT8 clk_index)
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{
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//temp code, will be switch to sdcard_driver.c
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*((volatile unsigned long *) (0x44010000+0x9*4)) = (((*((volatile unsigned long *) (0x44010000+0x9*4))) & (~0x3C000)) | ((clk_index) << 14));
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}
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#else
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static void beken_sdcard_set_clk_div(UINT8 clkdiv)
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{
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UINT32 reg;
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reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
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reg &= ~(SDCARD_FIFO_SD_RATE_SELECT_MASK << SDCARD_FIFO_SD_RATE_SELECT_POSI);
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reg |= ((clkdiv & SDCARD_FIFO_SD_RATE_SELECT_MASK)
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<< SDCARD_FIFO_SD_RATE_SELECT_POSI);
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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}
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void sdio_set_clock(UINT8 clk_index)
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{
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beken_sdcard_set_clk_div(clk_index);
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}
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#endif
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#if (CONFIG_SOC_BK7256XX)
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#if (CONFIG_PIN_SDIO_GROUP_0)
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#define PIN_ID_SDIO_CLK (GPIO_14)
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#define PIN_ID_SDIO_CMD (GPIO_15)
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#define PIN_ID_SDIO_D0 (GPIO_16)
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#define PIN_ID_SDIO_D1 (GPIO_17)
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#define PIN_ID_SDIO_D2 (GPIO_18)
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#define PIN_ID_SDIO_D3 (GPIO_19)
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#else
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#define PIN_ID_SDIO_CLK (GPIO_2)
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#define PIN_ID_SDIO_CMD (GPIO_3)
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#define PIN_ID_SDIO_D0 (GPIO_4)
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#define PIN_ID_SDIO_D1 (GPIO_5)
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#define PIN_ID_SDIO_D2 (GPIO_10)
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#define PIN_ID_SDIO_D3 (GPIO_11)
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#endif
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void sdio_gpio_config(void)
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{
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gpio_dev_unmap(PIN_ID_SDIO_CLK);
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gpio_dev_unmap(PIN_ID_SDIO_CMD);
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gpio_dev_unmap(PIN_ID_SDIO_D0);
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#if CONFIG_SDCARD_BUSWIDTH_4LINE
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gpio_dev_unmap(PIN_ID_SDIO_D1);
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gpio_dev_unmap(PIN_ID_SDIO_D2);
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gpio_dev_unmap(PIN_ID_SDIO_D3);
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#endif
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gpio_dev_map(PIN_ID_SDIO_CLK, GPIO_DEV_SDIO_HOST_CLK);
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bk_gpio_pull_up(PIN_ID_SDIO_CLK);
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bk_gpio_set_capacity(PIN_ID_SDIO_CLK, 3);
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gpio_dev_map(PIN_ID_SDIO_CMD, GPIO_DEV_SDIO_HOST_CMD);
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bk_gpio_pull_up(PIN_ID_SDIO_CMD);
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bk_gpio_set_capacity(PIN_ID_SDIO_CMD, 3);
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gpio_dev_map(PIN_ID_SDIO_D0, GPIO_DEV_SDIO_HOST_DATA0);
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bk_gpio_pull_up(PIN_ID_SDIO_D0);
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bk_gpio_set_capacity(PIN_ID_SDIO_D0, 3);
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#if CONFIG_SDCARD_BUSWIDTH_4LINE
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gpio_dev_map(PIN_ID_SDIO_D1, GPIO_DEV_SDIO_HOST_DATA1);
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bk_gpio_pull_up(PIN_ID_SDIO_D1);
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bk_gpio_set_capacity(PIN_ID_SDIO_D1, 3);
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gpio_dev_map(PIN_ID_SDIO_D2, GPIO_DEV_SDIO_HOST_DATA2);
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bk_gpio_pull_up(PIN_ID_SDIO_D2);
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bk_gpio_set_capacity(PIN_ID_SDIO_D2, 3);
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gpio_dev_map(PIN_ID_SDIO_D3, GPIO_DEV_SDIO_HOST_DATA3);
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bk_gpio_pull_up(PIN_ID_SDIO_D3);
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bk_gpio_set_capacity(PIN_ID_SDIO_D3, 3);
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#endif
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}
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#if CONFIG_SOC_BK7256XX
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//1:clock always on, 0:auto gate
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void sdio_clk_gate_config(uint8_t enable)
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{
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uint32_t reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
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//os_printf("%s:reg=0x%x, en=%d\r\n", __func__, reg, enable);
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if(enable)
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reg |= (1<<SDIO_REG0XD_CLK_GATE_ON_POS);
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else
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reg &= ~(1<<SDIO_REG0XD_CLK_GATE_ON_POS);
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//reset the fifo realte status
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if(!enable) //auto gate
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reg &= ~(SDCARD_FIFO_RX_FIFO_RST | SDCARD_FIFO_TX_FIFO_RST | SDCARD_FIFO_SD_STA_RST);
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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}
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#endif
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void sdio_clk_config(UINT8 enable)
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{
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sys_drv_dev_clk_pwr_up(CLK_PWR_ID_SDIO, enable);
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}
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#else
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void sdio_gpio_config(void)
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{
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UINT32 param;
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#if (CONFIG_SOC_BK7251)
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#if (CFG_SD_HOST_INTF == CONFIG_SD1_HOST_INTF)
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param = GFUNC_MODE_SD1_HOST;
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#else
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param = GFUNC_MODE_SD_HOST;
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#endif
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#else
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#if (CFG_SD_HOST_INTF == CONFIG_SD1_HOST_INTF)
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param = GFUNC_MODE_SD1_HOST;
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#else
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param = GFUNC_MODE_SD_HOST;
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#endif
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#endif
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sddev_control(DD_DEV_TYPE_GPIO, CMD_GPIO_ENABLE_SECOND, ¶m);
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}
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void sdio_clk_config(UINT8 enable)
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{
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UINT32 param;
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UINT32 cmd;
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if (enable)
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cmd = CMD_CLK_PWR_UP;
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else
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cmd = CMD_CLK_PWR_DOWN;
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param = PWD_SDIO_CLK_BIT;
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sddev_control(DD_DEV_TYPE_ICU, cmd, ¶m);
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}
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#endif
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void sdio_register_reset(void)
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{
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UINT32 reg;
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/* Clear cmd rsp int bit */
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, reg);
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/* Clear tx/rx fifo */
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reg = SDCARD_FIFO_RX_FIFO_RST | SDCARD_FIFO_TX_FIFO_RST;
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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/* Disabe all sdio interrupt */
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reg = 0;
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_MASK, reg);
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/* Config tx/rx fifo threshold */
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reg = ((SDCARD_RX_FIFO_THRD & SDCARD_FIFO_RX_FIFO_THRESHOLD_MASK)
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<< SDCARD_FIFO_RX_FIFO_THRESHOLD_POSI)
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| ((SDCARD_TX_FIFO_THRD & SDCARD_FIFO_TX_FIFO_THRESHOLD_MASK)
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<< SDCARD_FIFO_TX_FIFO_THRESHOLD_POSI);
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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#if (CONFIG_SOC_BK7256XX)
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reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg | (1<<SDIO_REG0XD_CLK_REC_SEL_POS));
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#endif
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}
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#if 0
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void sdio_register_reenable(void)
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{
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UINT32 reg;
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, reg);
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reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
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reg |= (SDCARD_FIFO_RX_FIFO_RST | SDCARD_FIFO_TX_FIFO_RST | SDCARD_FIFO_SD_STA_RST);
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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rtos_delay_milliseconds(5);
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/*Config tx/rx fifo threshold*/
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reg = ((SDCARD_RX_FIFO_THRD & SDCARD_FIFO_RX_FIFO_THRESHOLD_MASK)
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<< SDCARD_FIFO_RX_FIFO_THRESHOLD_POSI)
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| ((SDCARD_TX_FIFO_THRD & SDCARD_FIFO_TX_FIFO_THRESHOLD_MASK)
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<< SDCARD_FIFO_TX_FIFO_THRESHOLD_POSI);
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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}
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#endif
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void sdio_sendcmd_function(UINT8 cmd_index, UINT32 flag,
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UINT32 timeout, VOID *arg)
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{
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UINT32 reg;
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flag &= CMD_FLAG_MASK;
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reg = (UINT32)arg;
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REG_WRITE(REG_SDCARD_CMD_SEND_AGUMENT, reg);
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reg = timeout;
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REG_WRITE(REG_SDCARD_CMD_RSP_TIMER, reg);
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reg = ((((UINT32)cmd_index)&SDCARD_CMD_SEND_CTRL_CMD_INDEX_MASK)
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<< SDCARD_CMD_SEND_CTRL_CMD_INDEX_POSI)
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| ((flag & SDCARD_CMD_SEND_CTRL_CMD_FLAGS_MASK)
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<< SDCARD_CMD_SEND_CTRL_CMD_FLAGS_POSI)
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| SDCARD_CMD_SEND_CTRL_CMD_START;
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REG_WRITE(REG_SDCARD_CMD_SEND_CTRL, reg);
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}
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SDIO_Error sdio_wait_cmd_response(UINT32 cmd)
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{
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UINT32 reg;
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#if (CONFIG_SOC_BK7256XX)
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uint32_t i_timeout = 0x1000000;
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#endif
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while (1) {
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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//wait until cmd response
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if (reg & (SDCARD_CMDRSP_NORSP_END_INT
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| SDCARD_CMDRSP_RSP_END_INT
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| SDCARD_CMDRSP_TIMEOUT_INT))
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break;
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#if (CONFIG_SOC_BK7256XX)
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i_timeout--;
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if(i_timeout == 0)
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{
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SDCARD_WARN("%s:cmd%d fatal err:no resp/end/timeout int\r\n", __func__, cmd);
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return SD_CMD_RSP_TIMEOUT;
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}
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#endif
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}
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_CMD_RSP);//clear the int flag
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if ((reg & SDCARD_CMDRSP_TIMEOUT_INT) /*||(reg&SDCARD_CMDRSP_NORSP_END_INT)*/) {
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if ((cmd != 1))
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SDCARD_WARN("sdcard cmd %d timeout,cmdresp_int_reg:0x%x\r\n", cmd, reg);
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return SD_CMD_RSP_TIMEOUT;
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}
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if (reg & SDCARD_CMDRSP_CMD_CRC_FAIL) {
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if ((cmd != 41) && (cmd != 2) && (cmd != 9) && (cmd != 1)) {
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SDCARD_WARN("sdcard cmd %d crcfail,cmdresp_int_reg:0x%x\r\n", cmd, reg);
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return SD_CMD_CRC_FAIL;
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}
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}
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//os_printf("%s cmd=%d\r\n", __func__, cmd);
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return SD_OK;
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}
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void sdio_get_cmdresponse_argument(UINT8 num, UINT32 *resp)
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{
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switch (num) {
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case 0:
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*resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT0);
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break;
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case 1:
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*resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT1);
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break;
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case 2:
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*resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT2);
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break;
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case 3:
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*resp = REG_READ(REG_SDCARD_CMD_RSP_AGUMENT3);
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break;
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default:
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break;
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}
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}
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void sdio_setup_data(UINT32 data_dir, UINT32 byte_len)
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{
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UINT32 reg;
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if (data_dir == SD_DATA_DIR_RD) {
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reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
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reg &= (3 << 21);
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reg |= 0x3ffff; // set fifo
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REG_WRITE(REG_SDCARD_FIFO_THRESHOLD, reg);
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reg = SDCARD_DATA_REC_CTRL_DATA_EN;
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} else
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reg = SDCARD_DATA_REC_CTRL_DATA_WR_DATA_EN;
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reg |= SDCARD_DATA_REC_CTRL_DATA_BYTE_SEL
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| ((byte_len & SDCARD_DATA_REC_CTRL_BLK_SIZE_MASK)
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<< SDCARD_DATA_REC_CTRL_BLK_SIZE_POSI)
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#ifdef CONFIG_SDCARD_BUSWIDTH_4LINE
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| SDCARD_DATA_REC_CTRL_DATA_BUS
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#endif
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;
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REG_WRITE(REG_SDCARD_DATA_REC_CTRL, reg);
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}
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void sdio_set_data_timeout(UINT32 timeout)
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{
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REG_WRITE(REG_SDCARD_DATA_REC_TIMER, timeout);
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}
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void driver_sdcard_recv_data_start(int timeout)
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{
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REG_WRITE(REG_SDCARD_DATA_REC_TIMER, timeout);
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#ifdef CONFIG_SDCARD_BUSWIDTH_4LINE
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REG_WRITE(REG_SDCARD_DATA_REC_CTRL, (0x1 | (1 << 2) | (512 << 4) | (1 << 17)));
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#else
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REG_WRITE(REG_SDCARD_DATA_REC_CTRL, (0x1 | (512 << 4) | (1 << 17)));
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#endif
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}
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SDIO_Error sdcard_wait_receive_data(UINT8 *receive_buf)
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{
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#define WAIT_MAX_CNT (0x1000000) //Temp code
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UINT32 reg, i = 0;
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while (1) {
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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if (reg & (SDCARD_CMDRSP_DATA_REC_END_INT
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| SDCARD_CMDRSP_DATA_CRC_FAIL
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| SDCARD_CMDRSP_DATA_TIME_OUT_INT))
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break;
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//Temp code
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i++;
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if((i >= WAIT_MAX_CNT) && (i % 0x100000 == 0))
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SDCARD_PRT("%s:i=%x,timeout\r\n", __func__, i);
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}
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_DATA_RSP);//clear the int flag
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if (reg & SDCARD_CMDRSP_DATA_TIME_OUT_INT)
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return SD_DATA_TIMEOUT;
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if (reg & SDCARD_CMDRSP_DATA_CRC_FAIL) {
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SDCARD_WARN("sdcard data crcfail,cmdresp_int_reg:0x%x\r\n", reg);
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return SD_DATA_CRC_FAIL;
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}
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for (i = 0; i < SD_DEFAULT_BLOCK_SIZE ;) {
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/* wait fifo data valid */
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while (1) {
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//software needn't handle dead-loop,hardware can garantee
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if (REG_READ(REG_SDCARD_FIFO_THRESHOLD)&SDCARD_FIFO_RXFIFO_RD_READY)
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break;
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}
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reg = REG_READ(REG_SDCARD_RD_DATA_ADDR);
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*(receive_buf + i++) = reg & 0xff;
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*(receive_buf + i++) = (reg >> 8) & 0xff;
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*(receive_buf + i++) = (reg >> 16) & 0xff;
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*(receive_buf + i++) = (reg >> 24) & 0xff;
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}
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return SD_OK;
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}
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#if 0
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SDIO_Error sdcard_write_data(UINT8 *writebuff, UINT32 block)
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{
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UINT32 i, j, reg, tmpval;
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i = 0;
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// 1. fill the first block to fifo and start write data enable
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while (REG_READ(REG_SDCARD_FIFO_THRESHOLD) & SDCARD_FIFO_TXFIFO_WR_READY) {
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tmpval = (writebuff[i] << 24) | (writebuff[i + 1] << 16) | (writebuff[i + 2] << 8) | writebuff[i + 3];
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REG_WRITE(REG_SDCARD_WR_DATA_ADDR, tmpval);
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i += 4;
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if (SD_DEFAULT_BLOCK_SIZE <= i)
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break;
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}
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_MASK);
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reg |= SDCARD_CMDRSP_TX_FIFO_EMPTY_MASK;
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_MASK, reg);
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REG_WRITE(REG_SDCARD_DATA_REC_TIMER, DEF_HIGH_SPEED_DATA_TIMEOUT * block);
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reg = (SD_DEFAULT_BLOCK_SIZE << SDCARD_DATA_REC_CTRL_BLK_SIZE_POSI) |
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SDCARD_DATA_REC_CTRL_DATA_MUL_BLK | SDCARD_DATA_REC_CTRL_DATA_BYTE_SEL |
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SDCARD_DATA_REC_CTRL_DATA_WR_DATA_EN
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#ifdef CONFIG_SDCARD_BUSWIDTH_4LINE
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| SDCARD_DATA_REC_CTRL_DATA_BUS
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#endif
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;
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REG_WRITE(REG_SDCARD_DATA_REC_CTRL, reg);
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#if CONFIG_SOC_BK7256XX
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#else
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do {
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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} while (!(reg & SDCARD_CMDRSP_TX_FIFO_NEED_WRITE));
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#endif
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// 2. write other blocks
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while (--block) {
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j = 0;
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while (j < SD_DEFAULT_BLOCK_SIZE) {
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if (REG_READ(REG_SDCARD_FIFO_THRESHOLD) & SDCARD_FIFO_TXFIFO_WR_READY) {
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tmpval = (writebuff[i] << 24) | (writebuff[i + 1] << 16) | (writebuff[i + 2] << 8) | writebuff[i + 3];
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REG_WRITE(REG_SDCARD_WR_DATA_ADDR, tmpval);
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i += 4;
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j += 4;
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}
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}
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do {
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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} while (!(reg & SDCARD_CMDRSP_DATA_WR_END_INT));
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REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SDCARD_CMDRSP_DATA_WR_END_INT);
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#if CONFIG_SOC_BK7256XX
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#else
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do {
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reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
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} while (!(reg & SDCARD_CMDRSP_TX_FIFO_NEED_WRITE));
|
|
#endif
|
|
|
|
if (2 != ((reg & SDCARD_CMDRSP_WR_STATU) >> 20))
|
|
return SD_ERROR;
|
|
}
|
|
|
|
// 3. after the last block,write zero
|
|
while (1) {
|
|
reg = REG_READ(REG_SDCARD_FIFO_THRESHOLD);
|
|
if (reg & SDCARD_FIFO_TXFIFO_WR_READY) {
|
|
REG_WRITE(REG_SDCARD_WR_DATA_ADDR, 0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// 4.wait and clear flag
|
|
do {
|
|
reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
|
|
} while (!(reg & SDCARD_CMDRSP_DATA_WR_END_INT));
|
|
REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SDCARD_CMDRSP_DATA_WR_END_INT);
|
|
|
|
if (2 != ((reg & SDCARD_CMDRSP_WR_STATU) >> 20))
|
|
return SD_ERROR;
|
|
|
|
return SD_OK;
|
|
}
|
|
|
|
SDIO_Error sdcard_wait_write_end(void)
|
|
{
|
|
UINT32 reg;
|
|
while (1) {
|
|
reg = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
|
|
if (reg & (SDCARD_CMDRSP_DATA_WR_END_INT
|
|
| SDCARD_CMDRSP_DATA_CRC_FAIL
|
|
| SDCARD_CMDRSP_DATA_TIME_OUT_INT))
|
|
break;
|
|
}
|
|
|
|
REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_DATA_RSP);//clear the int flag
|
|
|
|
if (reg & SDCARD_CMDRSP_DATA_TIME_OUT_INT)
|
|
return SD_DATA_TIMEOUT;
|
|
if (reg & SDCARD_CMDRSP_DATA_CRC_FAIL) {
|
|
SDCARD_WARN("sdcard write data crcfail,cmdresp_int_reg:0x%x\r\n", reg);
|
|
return SD_DATA_CRC_FAIL;
|
|
}
|
|
|
|
return SD_OK;
|
|
}
|
|
|
|
#endif
|
|
int wait_Receive_Data(void)
|
|
{
|
|
uint32 ret = SD_ERR_LONG_TIME_NO_RESPONS, status = 0;
|
|
uint32 start_tm = rtos_get_time();
|
|
while (1) {
|
|
if (rtos_get_time() > start_tm + 4000) { // 4s
|
|
ret = SD_ERR_LONG_TIME_NO_RESPONS;
|
|
break;
|
|
}
|
|
|
|
status = REG_READ(REG_SDCARD_CMD_RSP_INT_SEL);
|
|
if (status & SDCARD_CMDRSP_DATA_REC_END_INT) {
|
|
if (status & SDCARD_CMDRSP_DATA_CRC_FAIL) {
|
|
os_printf("aaa\r\n");
|
|
//ret = SD_DATA_CRC_FAIL;
|
|
ret = SD_OK;
|
|
} else
|
|
ret = SD_OK;
|
|
break;
|
|
} else if (status & SDCARD_CMDRSP_DATA_CRC_FAIL) {
|
|
ret = SD_DATA_CRC_FAIL;
|
|
break;
|
|
} else if (status & SDCARD_CMDRSP_DATA_TIME_OUT_INT) {
|
|
ret = SD_DATA_TIMEOUT;
|
|
break;
|
|
}
|
|
}
|
|
REG_WRITE(REG_SDCARD_CMD_RSP_INT_SEL, SD_DATA_RSP);/*< clear the int flag */
|
|
return ret;
|
|
}
|
|
|
|
#endif // CONFIG_SDCARD
|
|
// EOF
|
|
|