521 lines
16 KiB
C
521 lines
16 KiB
C
// Copyright 2020-2021 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <driver/qspi.h>
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#include <driver/qspi_flash.h>
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#include "qspi_hal.h"
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#include <driver/int.h>
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#include <os/mem.h>
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#include <driver/qspi.h>
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#include "qspi_driver.h"
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#include "qspi_hal.h"
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#include "qspi_statis.h"
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#include <driver/trng.h>
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#define FLASH_READ_ID_CMD 0x9F
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#define FLASH_WR_S0_S7_CMD 0x1
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#define FLASH_WR_S8_S15_CMD 0x31
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#define FLASH_RD_S0_S7_CMD 0x5
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#define FLASH_RD_S8_S15_CMD 0x35
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#define FLASH_WR_EN_CMD 0x6
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#define FLASH_WR_CMD 0x2
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#define FLASH_RD_CMD 0x3
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#define FLASH_QUAD_WR_CMD 0x32
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#define FLASH_QUAD_RD_CMD 0xeb
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#define FLASH_ERASE_SECTOR_CMD 0x20
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#define FLASH_PAGE_SIZE 0x100
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#define FLASH_PAGE_MASK (FLASH_PAGE_SIZE - 1)
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#define FLASH_SECTOR_SIZE 0x1000
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#define FLASH_STATUS_REG_SIZE 1
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#define FLASH_READ_ID_SIZE 4
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#define QSPI_FIFO_LEN_MAX 256
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#define FLASH_QE_DATA BIT(1)
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#define FLASH_PROTECT_NONE_DATA 0
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#define QSPI_CMD1_LEN 8
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static void bk_qspi_flash_wait_wip_done(qspi_id_t id);
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bk_err_t bk_qspi_flash_init(qspi_id_t id)
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{
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qspi_config_t config = {0};
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config.src_clk = QSPI_SCLK_480M;
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config.src_clk_div = 0x4;
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config.clk_div = 0x2;
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BK_LOG_ON_ERR(bk_qspi_init(id, &config));
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_deinit(qspi_id_t id)
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{
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BK_LOG_ON_ERR(bk_qspi_deinit(id));
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return BK_OK;
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}
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static void bk_qspi_flash_wren(qspi_id_t id) {
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qspi_cmd_t wren_cmd = {0};
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wren_cmd.device = QSPI_FLASH;
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wren_cmd.wire_mode = QSPI_1WIRE;
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wren_cmd.work_mode = INDIRECT_MODE;
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wren_cmd.op = QSPI_WRITE;
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wren_cmd.cmd = FLASH_WR_EN_CMD;
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wren_cmd.data_len = 0;
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BK_LOG_ON_ERR(bk_qspi_command(id, &wren_cmd));
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bk_qspi_flash_wait_wip_done(id);
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}
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uint32_t bk_qspi_flash_read_s0_s7(qspi_id_t id)
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{
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qspi_cmd_t read_status_cmd = {0};
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uint32_t status_reg_data = 0;
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read_status_cmd.device = QSPI_FLASH;
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read_status_cmd.wire_mode = QSPI_1WIRE;
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read_status_cmd.work_mode = INDIRECT_MODE;
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read_status_cmd.op = QSPI_READ;
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read_status_cmd.cmd = FLASH_RD_S0_S7_CMD;
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read_status_cmd.data_len = FLASH_STATUS_REG_SIZE;
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BK_LOG_ON_ERR(bk_qspi_command(id, &read_status_cmd));
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bk_qspi_read(id, &status_reg_data, FLASH_STATUS_REG_SIZE);
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QSPI_LOGD("[%s]: status_reg_data = 0x%x.\n", __func__, (uint8_t)status_reg_data);
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return status_reg_data;
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}
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uint32_t bk_qspi_flash_read_s8_s15(qspi_id_t id)
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{
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qspi_cmd_t read_status_cmd = {0};
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uint32_t status_reg_data = 0;
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read_status_cmd.device = QSPI_FLASH;
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read_status_cmd.wire_mode = QSPI_1WIRE;
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read_status_cmd.work_mode = INDIRECT_MODE;
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read_status_cmd.op = QSPI_READ;
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read_status_cmd.cmd = FLASH_RD_S8_S15_CMD;
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read_status_cmd.data_len = FLASH_STATUS_REG_SIZE;
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BK_LOG_ON_ERR(bk_qspi_command(id, &read_status_cmd));
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bk_qspi_read(id, &status_reg_data, FLASH_STATUS_REG_SIZE);
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QSPI_LOGD("[%s]: status_reg_data = 0x%x.\n", __func__, (uint8_t)status_reg_data);
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return status_reg_data;
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}
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bk_err_t bk_qspi_flash_write_s0_s7(qspi_id_t id, uint8_t status_reg_data)
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{
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qspi_cmd_t write_status_cmd = {0};
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bk_qspi_flash_wren(id);
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write_status_cmd.device = QSPI_FLASH;
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write_status_cmd.wire_mode = QSPI_1WIRE;
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write_status_cmd.work_mode = INDIRECT_MODE;
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write_status_cmd.op = QSPI_WRITE;
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write_status_cmd.cmd = (status_reg_data << QSPI_CMD1_LEN) | FLASH_WR_S0_S7_CMD;
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write_status_cmd.data_len = 0;
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BK_LOG_ON_ERR(bk_qspi_command(id, &write_status_cmd));
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QSPI_LOGI("[%s]: status_reg_data to be writen is 0x%x.\n", __func__, status_reg_data);
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bk_qspi_flash_wait_wip_done(id);
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_write_s8_s15(qspi_id_t id, uint8_t status_reg_data)
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{
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qspi_cmd_t write_status_cmd = {0};
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bk_qspi_flash_wren(id);
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write_status_cmd.device = QSPI_FLASH;
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write_status_cmd.wire_mode = QSPI_1WIRE;
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write_status_cmd.work_mode = INDIRECT_MODE;
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write_status_cmd.op = QSPI_WRITE;
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write_status_cmd.cmd = (status_reg_data << QSPI_CMD1_LEN) | FLASH_WR_S8_S15_CMD;
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write_status_cmd.data_len = 0;
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BK_LOG_ON_ERR(bk_qspi_command(id, &write_status_cmd));
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QSPI_LOGI("[%s]: status_reg_data to be writen is 0x%x.\n", __func__, status_reg_data);
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bk_qspi_flash_wait_wip_done(id);
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_write_s0_s15(qspi_id_t id, uint16_t status_reg_data)
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{
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qspi_cmd_t write_status_cmd = {0};
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bk_qspi_flash_wren(id);
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write_status_cmd.device = QSPI_FLASH;
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write_status_cmd.wire_mode = QSPI_1WIRE;
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write_status_cmd.work_mode = INDIRECT_MODE;
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write_status_cmd.op = QSPI_WRITE;
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write_status_cmd.cmd = (status_reg_data << QSPI_CMD1_LEN) | FLASH_WR_S0_S7_CMD;
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write_status_cmd.data_len = 0;
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BK_LOG_ON_ERR(bk_qspi_command(id, &write_status_cmd));
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QSPI_LOGI("[%s]: status_reg_data to be writen is 0x%x.\n", __func__, status_reg_data);
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QSPI_LOGI("[%s]: write_status_cmd.cmd is 0x%x.\n", __func__, write_status_cmd.cmd);
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bk_qspi_flash_wait_wip_done(id);
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return BK_OK;
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}
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static void bk_qspi_flash_wait_wip_done(qspi_id_t id)
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{
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uint32_t status_reg_data = 0;
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for(int i = 0; i <= 2000; i++) {
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status_reg_data = bk_qspi_flash_read_s0_s7(id);
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if(0 == (status_reg_data & BIT(0))) {
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break;
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}
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if(i == 2000) {
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QSPI_LOGW("[%s]: wait write_in_progress done timeout.\n", __func__);
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}
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rtos_delay_milliseconds(1);
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}
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}
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bk_err_t bk_qspi_flash_erase_sector(qspi_id_t id, uint32_t addr)
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{
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qspi_cmd_t erase_sector_cmd = {0};
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bk_qspi_flash_wren(id);
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erase_sector_cmd.device = QSPI_FLASH;
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erase_sector_cmd.wire_mode = QSPI_1WIRE;
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erase_sector_cmd.work_mode = INDIRECT_MODE;
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erase_sector_cmd.op = QSPI_WRITE;
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erase_sector_cmd.cmd = FLASH_ERASE_SECTOR_CMD;
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erase_sector_cmd.addr = addr;
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BK_LOG_ON_ERR(bk_qspi_command(id, &erase_sector_cmd));
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bk_qspi_flash_wait_wip_done(id);
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_single_page_program(qspi_id_t id, uint32_t addr, const void *data, uint32_t size)
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{
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qspi_cmd_t page_program_cmd = {0};
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uint32_t cmd_data_len = 0;
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uint32_t *cmd_data = (uint32_t *)data;
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page_program_cmd.device = QSPI_FLASH;
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page_program_cmd.wire_mode = QSPI_1WIRE;
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page_program_cmd.work_mode = INDIRECT_MODE;
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page_program_cmd.op = QSPI_WRITE;
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page_program_cmd.cmd = FLASH_WR_CMD;
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while(0 < size) {
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bk_qspi_flash_wren(id);
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cmd_data_len = (size < QSPI_FIFO_LEN_MAX) ? size : QSPI_FIFO_LEN_MAX;
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bk_qspi_write(id, cmd_data, cmd_data_len);
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page_program_cmd.addr = addr;
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page_program_cmd.data_len = cmd_data_len;
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BK_LOG_ON_ERR(bk_qspi_command(id, &page_program_cmd));
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addr += cmd_data_len;
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cmd_data += cmd_data_len;
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size -= cmd_data_len;
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bk_qspi_flash_wait_wip_done(id);
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}
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_single_read(qspi_id_t id, uint32_t addr, void *data, uint32_t size)
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{
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qspi_cmd_t single_read_cmd = {0};
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uint32_t cmd_data_len = 0;
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uint32_t *cmd_data = data;
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single_read_cmd.device = QSPI_FLASH;
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single_read_cmd.wire_mode = QSPI_1WIRE;
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single_read_cmd.work_mode = INDIRECT_MODE;
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single_read_cmd.op = QSPI_READ;
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single_read_cmd.cmd = FLASH_RD_CMD;
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while(0 < size) {
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cmd_data_len = (size < QSPI_FIFO_LEN_MAX) ? size : QSPI_FIFO_LEN_MAX;
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single_read_cmd.addr = addr;
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single_read_cmd.data_len = cmd_data_len;
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BK_LOG_ON_ERR(bk_qspi_command(id, &single_read_cmd));
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bk_qspi_read(id, cmd_data, cmd_data_len);
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addr += cmd_data_len;
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cmd_data += cmd_data_len;
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size -= cmd_data_len;
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}
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_quad_page_program(qspi_id_t id, uint32_t addr, const void *data, uint32_t size)
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{
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qspi_cmd_t page_program_cmd = {0};
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uint32_t cmd_data_len = 0;
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uint32_t *cmd_data = (uint32_t *)data;
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page_program_cmd.device = QSPI_FLASH;
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page_program_cmd.wire_mode = QSPI_4WIRE;
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page_program_cmd.work_mode = INDIRECT_MODE;
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page_program_cmd.op = QSPI_WRITE;
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page_program_cmd.cmd = FLASH_QUAD_WR_CMD;
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while(0 < size) {
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bk_qspi_flash_wren(id);
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cmd_data_len = (size < QSPI_FIFO_LEN_MAX) ? size : QSPI_FIFO_LEN_MAX;
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bk_qspi_write(id, cmd_data, cmd_data_len);
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page_program_cmd.addr = addr;
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page_program_cmd.data_len = cmd_data_len;
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BK_LOG_ON_ERR(bk_qspi_command(id, &page_program_cmd));
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addr += cmd_data_len;
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cmd_data += cmd_data_len;
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size -= cmd_data_len;
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bk_qspi_flash_wait_wip_done(id);
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}
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_quad_read(qspi_id_t id, uint32_t addr, void *data, uint32_t size)
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{
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qspi_cmd_t quad_read_cmd = {0};
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uint32_t cmd_data_len = 0;
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uint32_t *cmd_data = data;
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quad_read_cmd.device = QSPI_FLASH;
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quad_read_cmd.wire_mode = QSPI_4WIRE;
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quad_read_cmd.work_mode = INDIRECT_MODE;
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quad_read_cmd.op = QSPI_READ;
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quad_read_cmd.cmd = FLASH_QUAD_RD_CMD;
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quad_read_cmd.dummy_cycle = 4;
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while(0 < size) {
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cmd_data_len = (size < QSPI_FIFO_LEN_MAX) ? size : QSPI_FIFO_LEN_MAX;
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quad_read_cmd.addr = addr;
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quad_read_cmd.data_len = cmd_data_len;
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BK_LOG_ON_ERR(bk_qspi_command(id, &quad_read_cmd));
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bk_qspi_read(id, cmd_data, cmd_data_len);
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addr += cmd_data_len;
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cmd_data += cmd_data_len;
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size -= cmd_data_len;
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}
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_write(qspi_id_t id, uint32_t base_addr, const void *data, uint32_t size)
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{
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uint8_t buf[QSPI_FIFO_LEN_MAX] = {0};
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uint32_t left_len = size;
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uint32_t write_len= 0;
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uint32_t write_addr = 0;
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uint32_t offset = 0;
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uint32_t page_write_len = 0;
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if(0 != (base_addr & FLASH_PAGE_MASK)) {
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write_addr = base_addr & (~FLASH_PAGE_MASK);
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bk_qspi_flash_quad_read(id, write_addr, buf, QSPI_FIFO_LEN_MAX);
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page_write_len = (QSPI_FIFO_LEN_MAX - (base_addr & FLASH_PAGE_MASK));
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write_len = (page_write_len > left_len) ? left_len : page_write_len;
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os_memcpy(buf + (base_addr & FLASH_PAGE_MASK), data, write_len);
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bk_qspi_flash_quad_page_program(id, write_addr, buf, QSPI_FIFO_LEN_MAX);
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offset += write_len;
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left_len -= write_len;
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if(left_len == 0) {
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return BK_OK;
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}
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}
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for (write_addr = base_addr + offset; write_addr < ((base_addr + size) & (~FLASH_PAGE_MASK)); write_addr += write_len) {
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write_len = (left_len > QSPI_FIFO_LEN_MAX) ? QSPI_FIFO_LEN_MAX : left_len;
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bk_qspi_flash_quad_page_program(id, write_addr, data + offset, write_len);
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offset += write_len;
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left_len -= write_len;
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}
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if(left_len == 0) {
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return BK_OK;
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}
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if(0 != ((base_addr + size) & FLASH_PAGE_MASK)) {
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bk_qspi_flash_quad_read(id, write_addr, buf, QSPI_FIFO_LEN_MAX);
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write_len = (base_addr + size) & FLASH_PAGE_MASK;
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os_memcpy(buf, data + offset, write_len);
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bk_qspi_flash_quad_page_program(id, write_addr, buf, write_len);
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}
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return BK_OK;
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}
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bk_err_t bk_qspi_flash_read(qspi_id_t id, uint32_t base_addr, void *data, uint32_t size)
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{
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uint8_t buf[QSPI_FIFO_LEN_MAX] = {0};
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uint32_t left_len = size;
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uint32_t read_len= 0;
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uint32_t offset = 0;
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for (uint32_t addr = base_addr; addr < (base_addr + size); addr += QSPI_FIFO_LEN_MAX) {
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offset += read_len;
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read_len = (left_len >= QSPI_FIFO_LEN_MAX) ? QSPI_FIFO_LEN_MAX : left_len;
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bk_qspi_flash_quad_read(id, addr, buf, QSPI_FIFO_LEN_MAX);
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os_memcpy(data + offset, buf, read_len);
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left_len -= QSPI_FIFO_LEN_MAX;
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}
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return BK_OK;
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}
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void bk_qspi_flash_quad_enable(qspi_id_t id) {
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uint32_t status_reg_data = 0;
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status_reg_data = (uint8_t)bk_qspi_flash_read_s8_s15(id);
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status_reg_data |= FLASH_QE_DATA;
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#if CONFIG_QSPI_FLASH_GD
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bk_qspi_flash_write_s8_s15(id, status_reg_data);
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#else
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status_reg_data = (status_reg_data << 8);
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bk_qspi_flash_write_s0_s15(id, status_reg_data);
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#endif
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bk_qspi_flash_read_s8_s15(id);
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}
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void bk_qspi_flash_set_protect_none(qspi_id_t id) {
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uint32_t status_reg_data = 0;
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status_reg_data = bk_qspi_flash_read_s0_s7(id);
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status_reg_data &= FLASH_PROTECT_NONE_DATA;
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bk_qspi_flash_write_s0_s7(id, status_reg_data);
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}
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uint32_t bk_qspi_flash_read_id(qspi_id_t id) {
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qspi_cmd_t read_id_cmd = {0};
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uint32_t read_id_data = 0;
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read_id_cmd.device = QSPI_FLASH;
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read_id_cmd.wire_mode = QSPI_1WIRE;
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read_id_cmd.work_mode = INDIRECT_MODE;
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read_id_cmd.op = QSPI_READ;
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read_id_cmd.cmd = FLASH_READ_ID_CMD;
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read_id_cmd.data_len = FLASH_READ_ID_SIZE;
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BK_LOG_ON_ERR(bk_qspi_command(id, &read_id_cmd));
|
|
|
|
bk_qspi_read(id, &read_id_data, FLASH_READ_ID_SIZE);
|
|
|
|
return read_id_data;
|
|
}
|
|
|
|
void qspi_flash_test_case(qspi_id_t id, uint32_t base_addr, void *data, uint32_t size)
|
|
{
|
|
uint32_t read_id = 0;
|
|
uint32_t *read_data = (uint32_t *)os_zalloc(size);
|
|
uint32_t *origin_data = (uint32_t *)data;
|
|
if (read_data == NULL) {
|
|
QSPI_LOGE("send buffer malloc failed\r\n");
|
|
return;
|
|
}
|
|
|
|
read_id = bk_qspi_flash_read_id(id);
|
|
QSPI_LOGI("%s read_id = 0x%x\n", __func__, read_id);
|
|
|
|
bk_qspi_flash_set_protect_none(id);
|
|
bk_qspi_flash_quad_enable(id);
|
|
|
|
/* quad write, then quad/single read to check data*/
|
|
bk_qspi_flash_erase_sector(id, base_addr);
|
|
bk_qspi_flash_read(id, base_addr, read_data, size);
|
|
|
|
for (int i = 0; i < size/4; i++) {
|
|
if(read_data[i] != 0xFFFFFFFF) {
|
|
QSPI_LOGI("[ERASE ERROR]: read_data[%d]=0x%x, should be 0xFFFFFFFF\n", i, read_data[i]);
|
|
}
|
|
QSPI_LOGD("[ERASE DBG]: read_data[%d]=0x%x, should be 0xFFFFFFFF\n", i, read_data[i]);
|
|
}
|
|
|
|
bk_qspi_flash_write(id, base_addr, data, size);
|
|
bk_qspi_flash_read(id, base_addr, read_data, size);
|
|
for (int i = 0; i < size/4; i++) {
|
|
if(read_data[i] != origin_data[i]) {
|
|
QSPI_LOGI("[QUAD WRITE - QUAD READ ERROR]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
QSPI_LOGD("[QUAD WRITE - QUAD READ DBG]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
|
|
bk_qspi_flash_single_read(id, base_addr, read_data, size);
|
|
for (int i = 0; i < size/4; i++) {
|
|
if(read_data[i] != origin_data[i]) {
|
|
QSPI_LOGI("[QUAD WRITE - SINGLE READ ERROR]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
QSPI_LOGD("[QUAD WRITE - SINGLE READ DBG]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
|
|
/* singel write, then single/quad read to check data*/
|
|
bk_qspi_flash_erase_sector(id, base_addr);
|
|
bk_qspi_flash_single_read(id, base_addr, read_data, size);
|
|
for (int i = 0; i < size/4; i++) {
|
|
if(read_data[i] != 0xFFFFFFFF) {
|
|
QSPI_LOGI("[ERASE ERROR]: read_data[%d]=0x%x, should be 0xFFFFFFFF\n", i, read_data[i]);
|
|
}
|
|
QSPI_LOGD("[ERASE DBG]: read_data[%d]=0x%x, should be 0xFFFFFFFF\n", i, read_data[i]);
|
|
}
|
|
|
|
bk_qspi_flash_single_page_program(id, base_addr, data, size);
|
|
bk_qspi_flash_single_read(id, base_addr, read_data, size);
|
|
for (int i = 0; i < size/4; i++) {
|
|
if(read_data[i] != origin_data[i]) {
|
|
QSPI_LOGI("[SINGLE WRITE - SINGLE READ ERROR]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
QSPI_LOGD("[SINGLE WRITE - SINGLE READ DBG]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
|
|
bk_qspi_flash_read(id, base_addr, read_data, size);
|
|
for (int i = 0; i < size/4; i++) {
|
|
if(read_data[i] != origin_data[i]) {
|
|
QSPI_LOGI("[SINGLE WRITE - QUAD READ ERROR]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
QSPI_LOGD("[SINGLE WRITE - QUAD READ DBG]: read_data[%d]=0x%x, origin data[%d]=0x%x\n", i, read_data[i], i, origin_data[i]);
|
|
}
|
|
|
|
if (read_data) {
|
|
os_free(read_data);
|
|
read_data = NULL;
|
|
}
|
|
}
|
|
|
|
void test_qspi_flash(qspi_id_t id, uint32_t base_addr, uint32_t buf_len)
|
|
{
|
|
uint32_t *send_data = (uint32_t *)os_zalloc(buf_len);
|
|
// uint32_t rand_val = bk_rand() % (0x100000000);
|
|
|
|
if (send_data == NULL) {
|
|
QSPI_LOGE("send buffer malloc failed\r\n");
|
|
return;
|
|
}
|
|
for (int i = 0; i < (buf_len/4); i++) {
|
|
send_data[i] = (0x03020100 + i*0x04040404) & 0xffffffff;
|
|
}
|
|
qspi_flash_test_case(id, base_addr, send_data, buf_len);
|
|
|
|
if (send_data) {
|
|
os_free(send_data);
|
|
send_data = NULL;
|
|
}
|
|
}
|