57 lines
1.8 KiB
C
Executable File
57 lines
1.8 KiB
C
Executable File
#ifndef __FLASH_BYPASS_H__
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#define __FLASH_BYPASS_H__
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CURRENT_ROUTINE_TEXT_SIZE (0x400)
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/*Write Enable for Status Register*/
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#define FLASH_CMD_WR_EN_SR (0x6)
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#define FLASH_CMD_WR_DISABLE (0x04)
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/*Write Status Register*/
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#define FLASH_CMD_WR_SR (0x31)
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/*Others*/
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#define FLASH_CMD_QUAD_IO_FAST_READ (0xEB)
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#define FLASH_GD25Q32C_SR_QUAD_EN (0x2)
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#define FLASH_CMD_ENTER_DEEP_PWR_DW (0xB9)
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#define FLASH_CMD_EXIT_DEEP_PWR_DW (0xAB)
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/*SYS regs define*/
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#define SYS_R_ADD_X(x) (0x44010000+((x)*4))
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/*SPI0 regs define*/
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#define SPI_CFG_TRX_LEN_MASK (0xffffU)
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#define SPI_CFG_TX_TRAHS_LEN_POSI (8)
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#define SPI_CFG_RX_TRAHS_LEN_POSI (20)
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#define SPI_CFG_RX_FIN_INT_EN (BIT(3))
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#define SPI_CFG_TX_FIN_INT_EN (BIT(2))
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#define SPI_CFG_RX_EN (BIT(1))
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#define SPI_CFG_TX_EN (BIT(0))
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#define SPI_CFG_TX_EN_ONE_BYTE (0x10D)
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#define SPI_CFG_TX_EN_TWO_BYTE (0x20D)
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#define SPI_STATUS_TX_FINISH_INT (BIT(13))
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#define SPI_STATUS_TXFIFO_WR_READY (BIT(1))
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#define SPI_STATUS_RXFIFO_RD_READY (BIT(2))
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#define FLASH_ID_GD25Q32C (0xC84016)
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#define FLASH_ID_TH25Q64 (0xCD6017)
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#define QE_RETRY_TIMES (10)
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#if CONFIG_SOC_BK7236XX
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__attribute__((section(".itcm_sec_code"))) int flash_bypass_op_write(uint8_t *op_code, uint8_t *tx_buf, uint32_t tx_len);
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#else
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__attribute__((section(".itcm_sec_code"))) void flash_bypass_quad_enable(void);
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__attribute__((section(".itcm_sec_code"))) void flash_bypass_quad_test(uint32_t quad_enable, uint32_t delay_cycle1, uint32_t delay_cycle2);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif //__FLASH_BYPASS_H__
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// eof
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