359 lines
8.7 KiB
Plaintext
Executable File
359 lines
8.7 KiB
Plaintext
Executable File
/*
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* Copyright (C), 2018-2019, Arm Technology (China) Co., Ltd.
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* All rights reserved
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*
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* The content of this file or document is CONFIDENTIAL and PROPRIETARY
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* to Arm Technology (China) Co., Ltd. It is subject to the terms of a
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* License Agreement between Licensee and Arm Technology (China) Co., Ltd
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* restricting among other things, the use, reproduction, distribution
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* and transfer. Each of the embodiments, including this information and,,
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* any derivative work shall retain this copyright notice.
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*/
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#include "soc/bk7258/reg_base.h"
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#include "partitions.h"
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#include "sdkconfig.h"
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OUTPUT_FORMAT("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
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__MSP_STACK_SIZE = (4 << 10);
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__MIN_HEAP_SIZE = (32 << 10);
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__MPU_PROTECT_SIZE = 0x0;
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__SWAP_SIZE = (2048);
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#if CONFIG_CPU0_SRAM_BASE
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__PRIMARY_APP_RAM_BASE = CONFIG_CPU0_SRAM_BASE;
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#else
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__PRIMARY_APP_RAM_BASE = SOC_SRAM0_DATA_BASE;
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#endif
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#if CONFIG_LV_ATTRIBUTE_FAST_MEM_L2
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__LVGL_SRAM_CODE_SIZE = 0x1000;
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#else
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__LVGL_SRAM_CODE_SIZE = 0;
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#endif
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MEMORY
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{
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FLASH (rx) : ORIGIN = (SOC_FLASH_DATA_BASE + CONFIG_PRIMARY_CPU1_APP_VIRTUAL_CODE_START), LENGTH = CONFIG_PRIMARY_CPU1_APP_VIRTUAL_CODE_SIZE
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RAM (rwx) : ORIGIN = __PRIMARY_APP_RAM_BASE + CONFIG_CPU0_SPE_RAM_SIZE, LENGTH = CONFIG_CPU1_APP_RAM_SIZE
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#if CONFIG_LV_ATTRIBUTE_FAST_MEM_L2
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LVGL_SRAM_CODE (rx) : ORIGIN = SOC_SRAM5_DATA_BASE, LENGTH = __LVGL_SRAM_CODE_SIZE
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#endif
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LVGL (rwx) : ORIGIN = (SOC_SRAM5_DATA_BASE + __LVGL_SRAM_CODE_SIZE), LENGTH = 0x20000 - __LVGL_SRAM_CODE_SIZE
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ITCM (rwx) : ORIGIN = SOC_ITCM_DATA_BASE + __MPU_PROTECT_SIZE, LENGTH = CONFIG_ITCM_SIZE - __MPU_PROTECT_SIZE
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DTCM (rwx) : ORIGIN = SOC_DTCM_DATA_BASE, LENGTH = CONFIG_DTCM_SIZE
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SWAP (rwx) : ORIGIN = __PRIMARY_APP_RAM_BASE + CONFIG_CPU0_SPE_RAM_SIZE - __SWAP_SIZE, LENGTH = __SWAP_SIZE
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PSRAM (rwx) : ORIGIN = SOC_PSRAM_DATA_BASE, LENGTH = 0x4000000
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#if CONFIG_LV_CODE_LOAD_PSRAM
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LVGL_PSRAM_CODE (rx) : ORIGIN = 0x60900000, LENGTH = 0x50000
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#endif
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}
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ENTRY(Reset_Handler)
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SECTIONS
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{
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ASSERT((. == ALIGN(512)), "vector table address align fault.")
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.vectors :
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{
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__vector_table = .;
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KEEP(*(.vectors))
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. = ALIGN(128);
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} > FLASH
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.gnu.sgstubs ALIGN(32) : ALIGN(32)
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{
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*(.gnu.sgstubs*)
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. = ALIGN(32);
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} > FLASH
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.text :
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{
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. = ALIGN(4);
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_stext = .;
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. = ALIGN(4);
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__devconfig_start = .;
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*(".devconfig.*")
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KEEP(*(SORT_BY_NAME(".devconfig*")))
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__devconfig_end = .;
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. = ALIGN(4);
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__apps_start = .;
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KEEP (*(.apps_data))
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__apps_end = .;
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_etext = .;
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. = ALIGN(4);
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} > FLASH
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.a_device_null :
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{
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KEEP(*(.a_deviceobj_null))
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} > FLASH
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.a_devices :
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{
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__device_start = .;
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KEEP(*(.a_deviceobj_*))
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__device_end = .;
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} > FLASH
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.a_init_entries :
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{
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__a_init_start = .;
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KEEP(*(.a_init_entry_*))
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__a_init_end = .;
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} > FLASH
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.ARM.extab :
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{
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} > FLASH
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__exidx_start = .;
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.ARM.exidx :
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{
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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} > FLASH
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__exidx_end = .;
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.copy.table :
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{
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. = ALIGN(4);
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__copy_table_start__ = .;
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LONG (__etext)
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LONG (__iram_start__)
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LONG ((__data_end__ - __iram_start__) / 4)
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/* Add each additional data section here */
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LONG (__etext2)
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LONG (__data2_start__)
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LONG ((__data2_end__ - __data2_start__) / 4)
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LONG (__dtcm_data)
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LONG (__dtcm_start__)
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LONG ((__dtcm_end__ - __dtcm_start__) / 4)
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LONG (__itcm_text)
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LONG (__itcm_start__)
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LONG ((__itcm_end__ - __itcm_start__) / 4)
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#if CONFIG_LV_CODE_LOAD_PSRAM
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LONG (__lvgl_psram_code)
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LONG (__lvgl_psram_code_start)
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LONG ((__lvgl_psram_code_end - __lvgl_psram_code_start) / 4)
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#endif
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#if CONFIG_LV_ATTRIBUTE_FAST_MEM_L2
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LONG (__lvgl_sram_code)
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LONG (__lvgl_sram_code_start)
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LONG ((__lvgl_sram_code_end - __lvgl_sram_code_start) / 4)
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#endif
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__copy_table_end__ = .;
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} > FLASH
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.zero.table :
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{
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. = ALIGN(4);
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__zero_table_start__ = .;
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LONG (_bss_start)
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LONG ((_bss_end - _bss_start) / 4)
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LONG (_heap_start)
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LONG ((_heap_end - _heap_start) / 4)
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/* Add each additional bss section here */
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LONG (__bss2_start__)
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LONG ((__bss2_end__ - __bss2_start__) / 4)
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LONG (__lvgl_start)
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LONG ((__lvgl_end - __lvgl_start) / 4)
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__zero_table_end__ = .;
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} > FLASH
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.itcm :
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{
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. = ALIGN(4);
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PROVIDE(__itcm_text = LOADADDR(.itcm));
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__itcm_start__ = .;
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KEEP(*(.null_trap_handler))
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*(.itcm)
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*(.itcm_section*)
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*(.itcm_sec_code*)
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*(.interrupt)
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. = ALIGN(4);
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__itcm_end__ = .;
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} > ITCM AT > FLASH
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.dtcm :
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{
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. = ALIGN(4);
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PROVIDE(__dtcm_data = LOADADDR(.dtcm));
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__dtcm_start__ = .;
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*(.dtcm)
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*(.dtcm_sec_data*)
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. = ALIGN(4);
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__dtcm_end__ = .;
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} > DTCM AT > FLASH
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.data :
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{
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. = ALIGN(512);
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PROVIDE(__etext = LOADADDR(.data));
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PROVIDE(__iram_flash_begin = LOADADDR(.data));
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__iram_start__ = .;
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. = ALIGN(512);
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__vector_itcm_table = .;
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KEEP(*(.vectors_iram))
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. = ALIGN(128);
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*(.iram)
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. = ALIGN(4);
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__iram_end__ = .;
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. = ALIGN(4);
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__data_start__ = .;
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*(.data)
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*(".data.*")
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*(.sdata)
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*(.gnu.linkonce.d*)
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. = ALIGN(4);
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__data_end__ = .;
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} > RAM AT > FLASH
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#if CONFIG_LV_CODE_LOAD_PSRAM
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.lvgl_psram_code :
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{
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. = ALIGN(4);
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PROVIDE(__lvgl_psram_code = LOADADDR(.lvgl_psram_code));
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__lvgl_psram_code_start = .;
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*(.text.lv_*)
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. = ALIGN(4);
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__lvgl_psram_code_end = .;
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} > LVGL_PSRAM_CODE AT > FLASH
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#endif
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#if CONFIG_LV_ATTRIBUTE_FAST_MEM_L2
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.lvgl_sram_code :
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{
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. = ALIGN(4);
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PROVIDE(__lvgl_sram_code = LOADADDR(.lvgl_sram_code));
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__lvgl_sram_code_start = .;
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*(.sram_sec_code*)
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. = ALIGN(4);
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__lvgl_sram_code_end = .;
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} > LVGL_SRAM_CODE AT > FLASH
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#endif
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_data_flash_begin = LOADADDR(.data);
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_data_ram_begin = ADDR(.data);
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_data_ram_end = .;
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s_rom_end = LOADADDR(.data) + SIZEOF(.data);
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.uninitialized (NOLOAD):
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{
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. = ALIGN(32);
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__uninitialized_start = .;
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*(.uninitialized)
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*(".uninitialized.*")
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KEEP(*(.keep.uninitialized))
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. = ALIGN(32);
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__uninitialized_end = .;
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} > RAM
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.bss (NOLOAD):
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{
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. = ALIGN(4);
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_bss_start = .;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_bss_end = .;
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} > RAM
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bss_size = _bss_end - _bss_start;
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.heap (COPY) :
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{
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. = ALIGN(8);
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_heap_start = .;
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. = . + (ORIGIN(RAM) + LENGTH(RAM) - __MSP_STACK_SIZE - _heap_start - 8); /* 16 bytes for boundary protection */
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. = ALIGN(8);
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_heap_end = .;
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} > RAM
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.stack (ORIGIN(RAM) + LENGTH(RAM) - __MSP_STACK_SIZE) (COPY) :
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{
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. = ALIGN(8);
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_sstack = .;
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__StackLimit = .;
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. = . + __MSP_STACK_SIZE;
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. = ALIGN(8);
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__StackTop = .;
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_estack = .;
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} > RAM
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.swap ORIGIN(SWAP):
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{
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. = ALIGN(8);
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_swap_start = .;
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* (.swap_data)
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* (.swap_data*)
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. = ALIGN(4);
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_swap_end = .;
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} > SWAP AT > FLASH
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.lvgl ORIGIN(LVGL) (NOLOAD):
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{
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. = ALIGN(4);
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__lvgl_start = .;
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*(.lvgl_draw)
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*(.lvgl_draw*)
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. = ALIGN(4);
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__lvgl_end = .;
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} > LVGL AT > FLASH
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.video.cache.data :
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{
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. = ALIGN(4);
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PROVIDE(__etext2 = LOADADDR(.video.cache.data));
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__data2_start__ = .;
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*(.video_cache_data)
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*(.video_cache_data*)
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. = ALIGN(4);
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__data2_end__ = .;
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} > PSRAM AT > FLASH
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.video_cache_bss (NOLOAD):
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{
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. = ALIGN(4);
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__bss2_start__ = .;
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*(.video_cache_bss)
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*(.video_cache_bss*)
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. = ALIGN(4);
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__bss2_end__ = .;
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} > PSRAM
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/* Set stack top to end of RAM, and stack limit move down by
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* size of stack_dummy section */
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__MSPTop = ORIGIN(RAM) + LENGTH(RAM);
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__MSPLimit = __MSPTop - __MSP_STACK_SIZE;
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ASSERT((s_rom_end < ORIGIN(FLASH) + LENGTH(FLASH)), "ROM overflow!!!")
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ASSERT(((ORIGIN(RAM) + LENGTH(RAM)) > (_heap_start + __MSP_STACK_SIZE + 8)), "Stack overflowed with bss")
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ASSERT(((_heap_end - _heap_start) >= __MIN_HEAP_SIZE), "Heap smaller than minimize size 32K!!!")
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}
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