112 lines
5.2 KiB
C
112 lines
5.2 KiB
C
#ifndef __PMU_H__
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#define __PMU_H__
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#define PMU_BASE (0x00800200)
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#define SCTRL_LOW_PWR_CLK (PMU_BASE + 0 * 4)
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#define LPO_CLK_MUX_POSI (0)
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#define LPO_CLK_MUX_MASK (0x3)
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#define LPO_SRC_ROSC (0x0)
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#define LPO_SRC_32K_XTAL (0x1)
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#define LPO_SRC_32K_DIV (0x2)
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#define SCTRL_SLEEP (PMU_BASE + 1 * 4)
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#define PROCORE_DLY_POSI (20)
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#define PROCORE_DLY_MASK (0xF)
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#define DCO_PWD_SLEEP_BIT (1 << 18)
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#define FLASH_PWD_SLEEP_BIT (1 << 17)
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#define ROSC_PWD_DEEPSLEEP_BIT (1 << 16)
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#define SLEEP_MODE_POSI (0)
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#define SLEEP_MODE_MASK (0xFFFF)
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#define SLEEP_MODE_CFG_NORMAL_VOL_WORD (0x4F89)
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#define SLEEP_MODE_CFG_LOW_VOL_WORD (0xB706)
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#define SLEEP_MODE_CFG_DEEP_WORD (0xADC1)
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#define SCTRL_DIGTAL_VDD (PMU_BASE + 2 * 4)
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#define DIG_VDD_ACTIVE_POSI (4)
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#define DIG_VDD_ACTIVE_MASK (0x7)
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#define DIG_VDD_SLEEP_POSI (0)
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#define DIG_VDD_SLEEP_MASK (0x7)
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#define VDD_1_DOT_51 (0x7)
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#define VDD_1_DOT_38 (0x6)
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#define VDD_1_DOT_25 (0x5)
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#define VDD_1_DOT_12 (0x4)
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#define VDD_0_DOT_99 (0x3)
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#define VDD_0_DOT_86 (0x2)
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#define VDD_0_DOT_73 (0x1)
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#define VDD_0_DOT_60 (0x0)
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#define SCTRL_PWR_MAC_MODEM (PMU_BASE + 3 * 4)
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#define MODEM_PWD_POSI (0)
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#define MODEM_PWD_MASK (0xFFFFU)
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#define MODEM_PWD (0xD802U)
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#define MODEM_PWU (0x0000U)
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#define SCTRL_DSP_PWR (PMU_BASE + 4 * 4)
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#define DSP_PWD_POSI (0)
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#define DSP_PWD_MASK (0xFFFF)
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#define DSP_PWD (0xD410)
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#define DSP_PWU (0x0000)
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#define ICU_TL410_CLK_PWD SCTRL_DSP_PWR //need_confirm
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#define TL410_CLK_PWD_VALUE (0xD410)
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#define SCTRL_BT_PWR (PMU_BASE + 5 * 4)
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#define BT_PWD_POSI (0)
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#define BT_PWD_MASK (0xFFFF)
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#define BT_PWD (0xDB1E)
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#define BT_PWU (0x0000)
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#define SCTRL_BLOCK_EN_CFG (PMU_BASE + 9 * 4)
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#define BLOCK_EN_WORD_POSI (20)
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#define BLOCK_EN_WORD_MASK (0xFFFUL)
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#define BLOCK_EN_WORD_PWD (0xA5CUL)
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#define BLOCK_EN_VALID_MASK (0xFFFFF)
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#define BLK_BIT_MIC_QSPI_RAM_OR_FLASH (1 << 19)
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#define BLK_BIT_LCD (1 << 18)
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#define BLK_BIT_AUDIO_PLL (1 << 17)
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#define BLK_BIT_AUDIO_RANDOM_GENERATOR (1 << 16)
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#define BLK_BIT_USB2 (1 << 15)
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#define BLK_BIT_USB (1 << 14)
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#define BLK_BIT_SARADC (1 << 13)
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#define BLK_BIT_TEMPRATURE_SENSOR (1 << 12)
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#define BLK_BIT_26M_XTAL_LOW_POWER (1 << 11)
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#define BLK_BIT_XTAL2RF (1 << 10)
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#define BLK_BIT_IO_LDO_LOW_POWER (1 << 09)
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#define BLK_BIT_ANALOG_SYS_LDO (1 << 08)
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#define BLK_BIT_DIGITAL_CORE_LDO_LOW_POWER (1 << 07)
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#define BLK_BIT_DIGITAL_CORE (1 << 06)
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#define BLK_BIT_DPLL_480M (1 << 05)
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#define BLK_BIT_32K_XTAL (1 << 04)
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#define BLK_BIT_26M_XTAL (1 << 03)
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#define BLK_BIT_ROSC32K (1 << 02)
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#define BLK_BIT_DCO (1 << 01)
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#define BLK_BIT_FLASH (1 << 00)
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#define SCTRL_PMU_STATUS (PMU_BASE + 6 * 4)
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#define SYNC_BUS_PWD_POSI (0)
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#define SYNC_BUS_PWD_MASK (0xFFFF)
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#define SYNC_BUS_PWD (0xD884)
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#define SYNC_BUS_PWU (0x0000)
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#define SCTRL_BLOCK_EN_MUX (PMU_BASE + 11 * 4)
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#define PMU_RTC_WKU (PMU_BASE + 15 * 4)
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#define PMU_CO_MCU_CONFIG (PMU_BASE + 0x13 * 4)
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#define BT_CLK_ENABLE (1 << 05)
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#define DSP_CLK_ENABLE (1 << 04)
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#define BT_SW_RESET_ENABLE (1 << 03)
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#define DSP_SW_RESET_ENABLE (1 << 02)
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#define BT_PROGRAM_DOWNLOAD_EN (1 << 01)
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#define DSP_PROGRAM_DOWNLOAD_EN (1 << 00)
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#define PMU_STATUS (PMU_BASE + 18 * 4)
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#define PMU_BAIS_CAL_OUT_POSI (12)
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#define PMU_BAIS_CAL_OUT_MASK (0x1F)
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#endif
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// eof
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