401 lines
11 KiB
C
Executable File
401 lines
11 KiB
C
Executable File
// Copyright 2020-2022 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _mailbox_channel_h_
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#define _mailbox_channel_h_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <common/bk_typedef.h>
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#include <driver/mailbox_types.h>
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#define SYSTEM_CPU_NUM CONFIG_CPU_CNT
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#define DST_CPU_ID_MASK 0xC0
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#define DST_CPU_ID_POS 6
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#define SRC_CPU_ID_MASK 0x30
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#define SRC_CPU_ID_POS 4
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#define LOG_CHNL_ID_MASK 0x0F
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#define GET_SRC_CPU_ID(log_chnl) (((log_chnl) & SRC_CPU_ID_MASK) >> SRC_CPU_ID_POS)
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#define GET_DST_CPU_ID(log_chnl) (((log_chnl) & DST_CPU_ID_MASK) >> DST_CPU_ID_POS)
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#define CPX_LOG_CHNL_START(src_cpu, dst_cpu) ((((dst_cpu) << DST_CPU_ID_POS) & DST_CPU_ID_MASK) + (((src_cpu) << SRC_CPU_ID_POS) & SRC_CPU_ID_MASK))
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#define GET_LOG_CHNL_ID(log_chnl) ((log_chnl) & LOG_CHNL_ID_MASK)
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/* ======================================================================================= */
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/* ========================== CPU0 --> Target_CPUs mailbox. =========================== */
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/* ======================================================================================= */
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#if CONFIG_SYS_CPU0
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#define SELF_CPU MAILBOX_CPU0
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enum
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{
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/* CPU0 --> CPU0 */
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CP0_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU0),
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CP0_MB_CHNL_CTRL = CP0_MB_LOG_CHNL_START,
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CP0_MB_LOG_CHNL_END,
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CP0_MB_LOG_CHNL_MAX = (CP0_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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/* the BIGGER the value, the LOWER the channel priority. */
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enum
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{
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/* CPU0 --> CPU1 */
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CP1_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU1),
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MB_CHNL_HW_CTRL = CP1_MB_LOG_CHNL_START,
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MB_CHNL_AUD,
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MB_CHNL_VID,
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MB_CHNL_PWC,
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MB_CHNL_MEDIA,
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MB_CHNL_MIPC_SYNC,
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MB_CHNL_LVGL,
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MB_CHNL_USB,
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MB_CHNL_AT,
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MB_CHNL_COM, /* MB_CHNL_COM is default mailbox channel used for audio and video */
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MB_CHNL_DEC,
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MB_CHNL_UART,
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MB_CHNL_FLASH,
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/* !!!!! Note !!!!! */
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/* ===> MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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MB_CHNL_LOG, /* MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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CP1_MB_LOG_CHNL_END,
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CP1_MB_LOG_CHNL_MAX = (CP1_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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/* the BIGGER the value, the LOWER the channel priority. */
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enum
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{
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/* CPU0 --> CPU2 */
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CP2_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU2),
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CP2_MB_CHNL_HW_CTRL = CP2_MB_LOG_CHNL_START,
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CP2_MB_CHNL_USB,
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CP2_MB_CHNL_LOG, /* MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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CP2_MB_LOG_CHNL_END,
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CP2_MB_LOG_CHNL_MAX = (CP1_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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#endif
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/* ======================================================================================= */
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/* ========================== CPU1 --> Target_CPUs mailbox. =========================== */
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/* ======================================================================================= */
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#if CONFIG_SYS_CPU1
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#define SELF_CPU MAILBOX_CPU1
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enum
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{
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/* CPU1 --> CPU0 */
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CP0_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU0),
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MB_CHNL_HW_CTRL = CP0_MB_LOG_CHNL_START,
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MB_CHNL_AUD,
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MB_CHNL_VID,
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MB_CHNL_PWC,
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MB_CHNL_MEDIA,
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MB_CHNL_MIPC_SYNC,
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MB_CHNL_LVGL,
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MB_CHNL_USB,
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MB_CHNL_AT,
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MB_CHNL_COM, /* MB_CHNL_COM is default mailbox channel used for audio and video */
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MB_CHNL_DEC,
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MB_CHNL_UART,
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MB_CHNL_FLASH,
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/* !!!!! Note !!!!! */
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/* ===> MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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MB_CHNL_LOG, /* MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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CP0_MB_LOG_CHNL_END,
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CP0_MB_LOG_CHNL_MAX = (CP0_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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/* the BIGGER the value, the LOWER the channel priority. */
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enum
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{
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/* CPU1 --> CPU1 */
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CP1_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU1),
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CP1_MB_CHNL_CTRL = CP1_MB_LOG_CHNL_START,
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CP1_MB_LOG_CHNL_END,
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CP1_MB_LOG_CHNL_MAX = (CP1_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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/* the BIGGER the value, the LOWER the channel priority. */
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enum
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{
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/* CPU1 --> CPU2 */
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CP2_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU2),
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CP2_MB_CHNL_CTRL = CP2_MB_LOG_CHNL_START,
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CP2_MB_CHNL_MEDIA,
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CP2_MB_CHNL_USB,
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CP2_MB_CHNL_MIPC,
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CP2_MB_LOG_CHNL_END,
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CP2_MB_LOG_CHNL_MAX = (CP2_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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#endif
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/* ======================================================================================= */
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/* ========================== CPU2 --> Target_CPUs mailbox. =========================== */
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/* ======================================================================================= */
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#if CONFIG_SYS_CPU2
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#define SELF_CPU MAILBOX_CPU2
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enum
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{
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/* CPU2 --> CPU0 */
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CP0_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU0),
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CP0_MB_CHNL_HW_CTRL = CP0_MB_LOG_CHNL_START,
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CP0_MB_CHNL_USB,
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// CP0_MB_CHNL_LOG, /* MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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CP0_MB_LOG_CHNL_END,
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CP0_MB_LOG_CHNL_MAX = (CP0_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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/* the BIGGER the value, the LOWER the channel priority. */
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enum
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{
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/* CPU2 --> CPU1 */
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CP1_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU1),
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CP1_MB_CHNL_CTRL = CP1_MB_LOG_CHNL_START,
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CP1_MB_CHNL_MEDIA,
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CP1_MB_CHNL_USB,
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CP1_MB_CHNL_MIPC,
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CP1_MB_CHNL_LOG, /* MB_CHNL_LOG should be the LAST one. LOWEST priority. */
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CP1_MB_LOG_CHNL_END,
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CP1_MB_LOG_CHNL_MAX = (CP1_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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/* the BIGGER the value, the LOWER the channel priority. */
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enum
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{
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/* CPU2 --> CPU2 */
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CP2_MB_LOG_CHNL_START = CPX_LOG_CHNL_START(SELF_CPU, MAILBOX_CPU2),
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CP2_MB_CHNL_CTRL = CP2_MB_LOG_CHNL_START,
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CP2_MB_LOG_CHNL_END,
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CP2_MB_LOG_CHNL_MAX = (CP2_MB_LOG_CHNL_START + LOG_CHNL_ID_MASK), // max 16 channels.
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};
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#endif
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#define SRC_CPU SELF_CPU
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#define CHNL_STATE_MASK 0xF
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#define CHNL_STATE_COM_FAIL 0x1 /* cmd NO target app, it is an ACK bit to peer CPU. */
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typedef union
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{
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struct
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{
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u32 cmd : 8;
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u32 state : 4;
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u32 Reserved : 20; /* reserved for system. */
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} ;
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u32 data;
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} mb_chnl_hdr_t;
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typedef struct
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{
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mb_chnl_hdr_t hdr;
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u32 param1;
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u32 param2;
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u32 param3;
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} mb_chnl_cmd_t;
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enum
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{
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ACK_STATE_PENDING = 0x01, /* cmd is being handled in the peer CPU. */
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ACK_STATE_COMPLETE, /* cmd handling is competed, addtional infos in ack_data1&ack_data2. */
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ACK_STATE_FAIL, /* cmd failed, addtional infos in ack_data1&ack_data2. */
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};
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typedef struct
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{
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mb_chnl_hdr_t hdr;
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u32 ack_data1;
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u32 ack_data2;
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union
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{
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u32 ack_data3;
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u32 ack_state; /* ack_state or ack_data3, depends on applications. */
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};
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} mb_chnl_ack_t;
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typedef void (* chnl_tx_cmpl_isr_t)(void *param, mb_chnl_ack_t *ack_buf);
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typedef void (* chnl_tx_isr_t)(void *param);
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/*
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* rx_isr firstly use the buf as the command buffer, after handled the cmd,
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* then use the buf as acknowledge buffer to fill the handle result.
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*/
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typedef void (* chnl_rx_isr_t)(void *param, mb_chnl_cmd_t *cmd_buf);
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enum
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{
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MB_CHNL_GET_STATUS = 0,
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MB_CHNL_SET_RX_ISR,
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MB_CHNL_SET_TX_ISR,
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MB_CHNL_SET_TX_CMPL_ISR,
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MB_CHNL_WRITE_SYNC,
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MB_CHNL_TX_RESET,
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};
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/*
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typedef struct // MB_CHNL_GET_STATUS cmd_param
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{
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u8 chnl_busy;
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} mb_chnl_get_status_param_t;
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typedef struct // MB_CHNL_SET_RX_ISR cmd_param
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{
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void * rx_isr;
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} mb_chnl_set_rx_isr_param_t;
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typedef struct // MB_CHNL_SET_TX_ISR cmd_param
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{
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void * tx_isr;
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} mb_chnl_set_tx_isr_param_t;
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typedef struct // MB_CHNL_SET_TX_CMPL_ISR cmd_param
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{
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void * tx_cmpl_isr;
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} mb_chnl_set_tx_cmpl_isr_param_t;
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*/
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/*
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* init logical chnanel module.
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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bk_err_t mb_chnl_init(void);
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/*
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* open logical chnanel.
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* input:
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* log_chnl : logical channel id to open.
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* callback_param : param passsed to all callbacks.
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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bk_err_t mb_chnl_open(u8 log_chnl, void * callback_param);
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/*
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* close logical chnanel.
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* input:
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* log_chnl : logical channel id to close.
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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bk_err_t mb_chnl_close(u8 log_chnl);
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/*
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* read from logical chnanel.
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* input:
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* log_chnl : logical channel id to read.
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* read_buf : buffer to receive channel cmd data.
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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bk_err_t mb_chnl_read(u8 log_chnl, mb_chnl_cmd_t * read_buf);
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/*
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* write to logical chnanel.
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* input:
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* log_chnl : logical channel id to write.
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* cmd_buf : command buffer to send.
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*
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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bk_err_t mb_chnl_write(u8 log_chnl, mb_chnl_cmd_t * cmd_buf);
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/*
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* logical chnanel misc io (set/get param).
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* input:
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* log_chnl : logical channel id to set/get param.
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* cmd : control command for logical channel.
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* param : parameter of the command.
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* MB_CHNL_GET_STATUS: param, (u8 *) point to buffer (one byte in size.) to receive status data.
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* MB_CHNL_SET_RX_ISR: param, pointer to rx_isr_callback.
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* MB_CHNL_SET_TX_ISR: param, pointer to tx_isr_callback.
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* MB_CHNL_SET_TX_CMPL_ISR: param, pointer to tx_cmpl_isr_callback.
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* MB_CHNL_WRITE_SYNC: param, pointer to mb_chnl_cmd_t buffer, write to mailbox synchronously.
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* MB_CHNL_TX_RESET: param is NULL.
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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bk_err_t mb_chnl_ctrl(u8 log_chnl, u8 cmd, void * param);
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/* ===================== physical channel APIs ==================*/
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/*
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* get communication statistics for target CPU (phy_chnl).
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* input:
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* dst_cpu : get statistics for this core.
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* output:
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* rx_cnt : if not NULL, return cmds count received by this core.
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* tx_cnt : if not NULL, return cmds count sent by this core.
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* return:
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* succeed: BK_OK;
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* failed : fail code.
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*
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*/
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void mb_chnl_get_statis(u8 dst_cpu, u32 *rx_cnt, u32 * tx_cnt);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _mailbox_channel_h_ */
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