363 lines
7.7 KiB
C
363 lines
7.7 KiB
C
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// Copyright 2020-2021 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <common/bk_include.h>
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#include "i2s_hal.h"
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#include "i2s_ll_macro_def.h"
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#include <driver/i2s_types.h>
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bk_err_t i2s_hal_config(const i2s_cfg_t *config)
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{
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i2s_ll_set_reg0x0_i2spcmen(config->i2s_en);
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i2s_ll_set_reg0x0_msten(config->role);
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i2s_ll_set_reg0x0_modesel(config->work_mode);
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i2s_ll_set_reg0x0_lrckrp(config->lrck_invert);
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i2s_ll_set_reg0x0_sclkinv(config->sck_invert);
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i2s_ll_set_reg0x0_lsbfirst(config->lsb_first_en);
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i2s_ll_set_reg0x0_synclen(config->sync_length);
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i2s_ll_set_reg0x0_datalen(config->data_length - 1);
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i2s_ll_set_reg0x0_pcm_dlen(config->pcm_dlength);
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i2s_ll_set_reg0x0_smpratio(config->sample_ratio);
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i2s_ll_set_reg0x0_bitratio(config->sck_ratio);
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i2s_ll_set_reg0x1_parallel_en(config->parallel_en);
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i2s_ll_set_reg0x1_lrcom_store(config->store_mode);
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i2s_ll_set_reg0x1_bitratio_h4b(config->sck_ratio_h4b);
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i2s_ll_set_reg0x1_smpratio_h2b(config->sample_ratio_h2b);
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i2s_ll_set_reg0x1_txint_level(config->txint_level);
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i2s_ll_set_reg0x1_rxint_level(config->rxint_level);
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return BK_OK;
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}
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bk_err_t i2s_hal_deconfig(void)
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{
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i2s_ll_set_reg0x0_value(0);
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i2s_ll_set_reg0x1_value(0);
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i2s_ll_set_reg0x3_value(0);
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i2s_ll_set_reg0x4_value(0);
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i2s_ll_set_reg0x5_rx2ovf(1);
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i2s_ll_set_reg0x5_tx2udf(1);
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i2s_ll_set_reg0x6_value(0);
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i2s_ll_set_reg0x7_value(0);
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i2s_ll_set_reg0x8_value(0);
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return BK_OK;
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}
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bk_err_t i2s_hal_int_status_get(i2s_int_status_t *int_status)
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{
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switch(int_status->channel_id)
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{
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case I2S_CHANNEL_1:
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int_status->tx_udf = (bool)i2s_ll_get_reg0x2_txudf();
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int_status->rx_ovf = (bool)i2s_ll_get_reg0x2_rxovf();
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int_status->tx_int = (bool)i2s_ll_get_reg0x2_txint();
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int_status->rx_int = (bool)i2s_ll_get_reg0x2_rxint();
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break;
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case I2S_CHANNEL_2:
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int_status->tx_udf = (bool)i2s_ll_get_reg0x5_tx2udf();
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int_status->rx_ovf = (bool)i2s_ll_get_reg0x5_rx2ovf();
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int_status->tx_int = (bool)i2s_ll_get_reg0x5_tx2int();
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int_status->rx_int = (bool)i2s_ll_get_reg0x5_rx2int();
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break;
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case I2S_CHANNEL_3:
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int_status->tx_udf = (bool)i2s_ll_get_reg0x5_tx3udf();
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int_status->rx_ovf = (bool)i2s_ll_get_reg0x5_rx3ovf();
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int_status->tx_int = (bool)i2s_ll_get_reg0x5_tx3int();
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int_status->rx_int = (bool)i2s_ll_get_reg0x5_rx3int();
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break;
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/*
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case I2S_CHANNEL_4:
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int_status->tx_udf = (bool)i2s_ll_get_reg0x5_tx4udf();
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int_status->rx_ovf = (bool)i2s_ll_get_reg0x5_rx4ovf();
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int_status->tx_int = (bool)i2s_ll_get_reg0x5_tx4int();
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int_status->rx_int = (bool)i2s_ll_get_reg0x5_rx4int();
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break;
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*/
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default:
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break;
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}
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return BK_OK;
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}
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bk_err_t i2s_hal_read_ready_get(uint32_t *read_flag)
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{
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*read_flag = i2s_ll_get_reg0x2_rxfifo_rd_ready();
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return BK_OK;
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}
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bk_err_t i2s_hal_write_ready_get(uint32_t *write_flag)
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{
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*write_flag = i2s_ll_get_reg0x2_txfifo_wr_ready();
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return BK_OK;
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}
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bk_err_t i2s_hal_en_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_i2spcmen(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_int_set(i2s_isr_id_t int_id, uint32_t value)
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{
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switch(int_id)
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{
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case I2S_ISR_CHL1_TXUDF:
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i2s_ll_set_reg0x1_txudf_en(value);
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break;
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case I2S_ISR_CHL1_RXOVF:
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i2s_ll_set_reg0x1_rxovf_en(value);
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break;
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case I2S_ISR_CHL1_TXINT:
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i2s_ll_set_reg0x1_txint_en(value);
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break;
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case I2S_ISR_CHL1_RXINT:
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i2s_ll_set_reg0x1_rxint_en(value);
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break;
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case I2S_ISR_CHL2_TXUDF:
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i2s_ll_set_reg0x4_tx2udf_en(value);
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break;
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case I2S_ISR_CHL2_RXOVF:
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i2s_ll_set_reg0x4_rx2ovf_en(value);
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break;
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case I2S_ISR_CHL2_TXINT:
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i2s_ll_set_reg0x4_tx2int_en(value);
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break;
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case I2S_ISR_CHL2_RXINT:
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i2s_ll_set_reg0x4_rx2int_en(value);
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break;
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case I2S_ISR_CHL3_TXUDF:
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i2s_ll_set_reg0x4_tx3udf_en(value);
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break;
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case I2S_ISR_CHL3_RXOVF:
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i2s_ll_set_reg0x4_rx3ovf_en(value);
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break;
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case I2S_ISR_CHL3_TXINT:
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i2s_ll_set_reg0x4_tx3int_en(value);
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break;
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case I2S_ISR_CHL3_RXINT:
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i2s_ll_set_reg0x4_rx3int_en(value);
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break;
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/*
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case I2S_ISR_CHL4_TXUDF:
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i2s_ll_set_reg0x4_tx4udf_en(value);
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break;
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case I2S_ISR_CHL4_RXOVF:
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i2s_ll_set_reg0x4_rx4ovf_en(value);
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break;
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case I2S_ISR_CHL4_TXINT:
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i2s_ll_set_reg0x4_tx4int_en(value);
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break;
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case I2S_ISR_CHL4_RXINT:
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i2s_ll_set_reg0x4_rx4int_en(value);
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break;
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*/
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default:
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break;
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}
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return BK_OK;
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}
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bk_err_t i2s_hal_role_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_msten(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_work_mode_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_modesel(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_lrck_invert_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_lrckrp(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_sck_invert_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_sclkinv(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_lsb_first_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_lsbfirst(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_sync_len_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_synclen(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_data_len_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_datalen(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_pcm_dlen_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_pcm_dlen(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_store_mode_set(uint32_t value)
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{
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i2s_ll_set_reg0x1_lrcom_store(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_rxfifo_clear(void)
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{
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i2s_ll_set_reg0x1_rxfifo_clr(1);
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return BK_OK;
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}
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bk_err_t i2s_hal_txfifo_clear(void)
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{
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i2s_ll_set_reg0x1_txfifo_clr(1);
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return BK_OK;
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}
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bk_err_t i2s_hal_txudf_int_clear(i2s_channel_id_t channel_id)
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{
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switch (channel_id)
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{
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case I2S_CHANNEL_1:
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i2s_ll_set_reg0x2_txudf(1);
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break;
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case I2S_CHANNEL_2:
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i2s_ll_set_reg0x5_tx2udf(1);
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break;
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case I2S_CHANNEL_3:
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i2s_ll_set_reg0x5_tx3udf(1);
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break;
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/*
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case I2S_CHANNEL_4:
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i2s_ll_set_reg0x5_tx4udf(1);
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break;
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*/
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default:
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break;
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}
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return BK_OK;
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}
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bk_err_t i2s_hal_rxovf_int_clear(i2s_channel_id_t channel_id)
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{
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switch (channel_id)
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{
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case I2S_CHANNEL_1:
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i2s_ll_set_reg0x2_rxovf(1);
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break;
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case I2S_CHANNEL_2:
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i2s_ll_set_reg0x5_rx2ovf(1);
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break;
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case I2S_CHANNEL_3:
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i2s_ll_set_reg0x5_rx3ovf(1);
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break;
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/*
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case I2S_CHANNEL_4:
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i2s_ll_set_reg0x5_rx4ovf(1);
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break;
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*/
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default:
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break;
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}
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return BK_OK;
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}
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bk_err_t i2s_hal_txint_level_set(uint32_t value)
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{
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i2s_ll_set_reg0x1_txint_level(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_rxint_level_set(uint32_t value)
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{
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i2s_ll_set_reg0x1_rxint_level(value);
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return BK_OK;
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}
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bk_err_t i2s_hal_data_write(uint32_t channel_id, uint32_t value)
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{
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switch(channel_id)
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{
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case 1:
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i2s_ll_set_reg0x3_i2s_dat(value);
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break;
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case 2:
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i2s_ll_set_reg0x6_value(value);
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break;
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case 3:
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i2s_ll_set_reg0x7_value(value);
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break;
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/*
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case 4:
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i2s_ll_set_reg0x8_value(value);
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break;
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*/
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default:
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break;
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}
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return BK_OK;
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}
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bk_err_t i2s_hal_data_read(uint32_t *value)
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{
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*value = i2s_ll_get_reg0x3_i2s_dat();
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return BK_OK;
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}
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bk_err_t i2s_hal_sample_ratio_set(uint32_t value)
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{
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i2s_ll_set_reg0x0_smpratio(value);
|
||
|
|
return BK_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
bk_err_t i2s_hal_sck_ratio_set(uint32_t value)
|
||
|
|
{
|
||
|
|
i2s_ll_set_reg0x0_bitratio(value);
|
||
|
|
return BK_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
bk_err_t i2s_hal_sample_ratio_h2b_set(uint32_t value)
|
||
|
|
{
|
||
|
|
i2s_ll_set_reg0x1_smpratio_h2b(value);
|
||
|
|
return BK_OK;
|
||
|
|
}
|
||
|
|
|
||
|
|
bk_err_t i2s_hal_sck_ratio_h4b_set(uint32_t value)
|
||
|
|
{
|
||
|
|
i2s_ll_set_reg0x1_bitratio_h4b(value);
|
||
|
|
return BK_OK;
|
||
|
|
}
|
||
|
|
|