105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
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// Copyright 2020-2021 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "dma_hal.h"
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#include "dma_ll.h"
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#define DMA_HAL_RETURN_ON_INVALID_ADDR(start_addr, end_addr) do {\
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if ((0 < (end_addr)) && ((end_addr) < (start_addr))) {\
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return BK_ERR_DMA_HAL_INVALID_ADDR;\
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}\
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} while(0)
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bk_err_t dma_hal_init(dma_hal_t *hal)
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{
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hal->hw = (dma_hw_t *)DMA_LL_REG_BASE(hal->id);
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//TODO:only CPU0 init hardware
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#if CONFIG_SYS_CPU0
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dma_ll_init(hal->hw);
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#endif
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dma_ll_set_prio_mode_round_robin(hal->hw);
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return BK_OK;
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}
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void dma_hal_init_without_channels(dma_hal_t *hal)
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{
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hal->hw = (dma_hw_t *)DMA_LL_REG_BASE(hal->id);
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//soft reset for all CPUs
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dma_ll_init_without_channels(hal->hw);
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}
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bk_err_t dma_hal_init_dma(dma_hal_t *hal, dma_id_t id, const dma_config_t *config)
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{
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DMA_HAL_RETURN_ON_INVALID_ADDR(config->src.start_addr, config->src.end_addr);
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DMA_HAL_RETURN_ON_INVALID_ADDR(config->dst.start_addr, config->dst.end_addr);
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dma_ll_set_work_mode(hal->hw, id, config->mode);
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dma_ll_set_chan_prio(hal->hw, id, config->chan_prio);
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dma_ll_set_dest_data_width(hal->hw, id, config->dst.width);
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dma_ll_set_src_data_width(hal->hw, id, config->src.width);
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dma_ll_set_dest_req_mux(hal->hw, id, config->dst.dev);
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dma_ll_set_src_req_mux(hal->hw, id, config->src.dev);
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#if CONFIG_GDMA_HW_V2PX
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dma_ll_set_pixel_trans_type(hal->hw, id, config->trans_type);
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dma_ll_set_dest_write_interval(hal->hw, id, config->dest_wr_intlv);
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dma_ll_set_src_read_interval(hal->hw, id, config->src_rd_intlv);
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#endif
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dma_ll_set_src_start_addr(hal->hw, id, config->src.start_addr);
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dma_ll_set_src_loop_addr(hal->hw, id, config->src.start_addr, config->src.end_addr);
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dma_ll_set_dest_start_addr(hal->hw, id, config->dst.start_addr);
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dma_ll_set_dest_loop_addr(hal->hw, id, config->dst.start_addr, config->dst.end_addr);
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if (config->src.addr_inc_en) {
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dma_ll_enable_src_addr_inc(hal->hw, id);
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} else {
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dma_ll_disable_src_addr_inc(hal->hw, id);
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}
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if (config->src.addr_loop_en) {
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dma_ll_enable_src_addr_loop(hal->hw, id);
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} else {
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dma_ll_disable_src_addr_loop(hal->hw, id);
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}
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if (config->dst.addr_inc_en) {
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dma_ll_enable_dest_addr_inc(hal->hw, id);
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} else {
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dma_ll_disable_dest_addr_inc(hal->hw, id);
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}
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if (config->dst.addr_loop_en) {
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dma_ll_enable_dest_addr_loop(hal->hw, id);
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} else {
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dma_ll_disable_dest_addr_loop(hal->hw, id);
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}
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return BK_OK;
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}
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bk_err_t dma_hal_start_common(dma_hal_t *hal, dma_id_t id)
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{
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dma_ll_enable(hal->hw, id);
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return BK_OK;
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}
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bk_err_t dma_hal_stop_common(dma_hal_t *hal, dma_id_t id)
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{
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dma_ll_clear_interrupt_status(hal->hw, id);
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dma_ll_disable(hal->hw, id);
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return BK_OK;
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}
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