432 lines
9.0 KiB
ArmAsm
432 lines
9.0 KiB
ArmAsm
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// Copyright 2020-2021 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "boot.h"
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#include "arm.h"
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#include "boot_asm_macro.h"
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.globl entry_main
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.globl boot_reset
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.globl boot_undefined
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.globl boot_pabort
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.globl boot_dabort
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.globl boot_reserved
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.globl do_undefined
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.globl do_pabort
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.globl do_dabort
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.globl do_reserved
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.globl boot_exception_undefine
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.globl boot_exception_prefetch_abort
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.globl boot_exception_data_abort
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.globl boot_exception_reserved
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.globl boot_stack_base_UNUSED
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.globl boot_stack_len_UNUSED
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.globl boot_stack_base_IRQ
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.globl boot_stack_len_IRQ
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.globl boot_stack_base_SVC
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.globl boot_stack_len_SVC
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.globl boot_stack_base_FIQ
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.globl boot_stack_len_FIQ
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.globl boot_stack_base_SYS
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.globl boot_stack_len_SYS
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/**
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* Context save and restore macro definitions
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*/
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.macro PUSH_ALL_ARM_REG
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BOOT_CHANGE_MODE BOOT_ARM_MODE_SYS BOOT_ARM_MODE_MASK
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LDR R1, = MCU_REG_BACKUP_TOP_SYS // get backup top.
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STMFD R1!, {R8-R14} // backup R8-R14
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MRS R0, CPSR
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STMFD R1!, {R0} // backup CPSR
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BOOT_CHANGE_MODE BOOT_ARM_MODE_IRQ BOOT_ARM_MODE_MASK
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LDR R1, = MCU_REG_BACKUP_TOP_IRQ // get backup top.
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STMFD R1!, {R8-R14} // backup R8-R14
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MRS R0, SPSR
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STMFD R1!, {R0} // backup SPSR
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MRS R0, CPSR
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STMFD R1!, {R0} // backup CPSR
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BOOT_CHANGE_MODE BOOT_ARM_MODE_FIQ BOOT_ARM_MODE_MASK
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LDR R1, = MCU_REG_BACKUP_TOP_FIQ // get backup top.
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STMFD R1!, {R8-R14} // backup R8-R14
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MRS R0, SPSR
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STMFD R1!, {R0} // backup SPSR
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MRS R0, CPSR
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STMFD R1!, {R0} // backup CPSR
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BOOT_CHANGE_MODE BOOT_ARM_MODE_ABT BOOT_ARM_MODE_MASK
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LDR R1, = MCU_REG_BACKUP_TOP_ABT // get backup top.
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STMFD R1!, {R8-R14} // backup R8-R14
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MRS R0, SPSR
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STMFD R1!, {R0} // backup SPSR
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MRS R0, CPSR
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STMFD R1!, {R0} // backup CPSR
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BOOT_CHANGE_MODE BOOT_ARM_MODE_UND BOOT_ARM_MODE_MASK
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LDR R1, = MCU_REG_BACKUP_TOP_UND // get backup top.
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STMFD R1!, {R8-R14} // backup R8-R14
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MRS R0, SPSR
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STMFD R1!, {R0} // backup SPSR
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MRS R0, CPSR
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STMFD R1!, {R0} // backup CPSR
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BOOT_CHANGE_MODE BOOT_ARM_MODE_SVC BOOT_ARM_MODE_MASK
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LDR R1, = MCU_REG_BACKUP_TOP_SVC // get backup top.
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STMFD R1!, {R8-R14} // backup R8-R14
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MRS R0, SPSR
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STMFD R1!, {R0} // backup SPSR
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MRS R0, CPSR
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STMFD R1!, {R0} // backup CPSR
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.endm
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/**
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* Macro for switching ARM mode
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*/
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.macro BOOT_CHANGE_MODE, mode, mode_mask
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MRS R0, CPSR
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BIC R0, R0, #\mode_mask
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ORR R0, R0, #\mode
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MSR CPSR_c, R0
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.endm
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/**
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* Macro for setting the stack
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*/
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.macro BOOT_SET_STACK, stackStart, stackLen, color
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LDR R0, \stackStart
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LDR R1, \stackLen
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ADD R1, R1, R0
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MOV SP, R1 //Set stack pointer
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LDR R2, =\color
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3:
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CMP R0, R1 //End of stack?
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STRLT R2, [r0] //Colorize stack word
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ADDLT R0, R0, #4
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BLT 3b //branch to previous local label
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.endm
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.section .bss
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.align 3
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.global fiq_stack_start
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fiq_stack_start:
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.space FIQ_STACK_SIZE
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.align 3
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.global irq_stack_start
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irq_stack_start:
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.space IRQ_STACK_SIZE
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.align 3
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.global und_stack_start
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und_stack_start:
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.space UND_STACK_SIZE
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.align 3
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.global sys_stack_start
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sys_stack_start:
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.space SYS_STACK_SIZE
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.align 3
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.global abt_stack_start
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abt_stack_start:
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.space ABT_STACK_SIZE
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.align 3
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.global svc_stack_start
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svc_stack_start:
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.space SVC_STACK_SIZE
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.section ".boot", "ax"
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boot_reset:
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//Disable IRQ and FIQ before starting anything
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MRS R0, CPSR
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ORR R0, R0, #0xC0
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MSR CPSR_c, R0
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/*Init the BSS section*/
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BL _sysboot_zi_init
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//Setup all stacks //Note: Abt and Usr mode are not used
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BOOT_CHANGE_MODE BOOT_ARM_MODE_SYS BOOT_ARM_MODE_MASK
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BOOT_SET_STACK boot_stack_base_SYS boot_stack_len_SYS BOOT_COLOR_SYS
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BOOT_CHANGE_MODE BOOT_ARM_MODE_ABT BOOT_ARM_MODE_MASK
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BOOT_SET_STACK boot_stack_base_UNUSED boot_stack_len_UNUSED BOOT_COLOR_UNUSED
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BOOT_CHANGE_MODE BOOT_ARM_MODE_UND BOOT_ARM_MODE_MASK
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BOOT_SET_STACK boot_stack_base_UNUSED boot_stack_len_UNUSED BOOT_COLOR_UNUSED
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//TODO optimize it, put the magic number to soc.h
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#if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A)
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B AFTER_FLAG
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.org 0xc0 //0x100 - sizeof(section.vector) = 0x100 - 0x40
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.word 0x32374B42
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.word 0x00003133
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AFTER_FLAG:
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#elif (CONFIG_SOC_BK7271)
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B AFTER_FLAG
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.org 0xc0
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.word 0x32374B42
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.word 0x00003137
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AFTER_FLAG:
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#endif
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BOOT_CHANGE_MODE BOOT_ARM_MODE_IRQ BOOT_ARM_MODE_MASK
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BOOT_SET_STACK boot_stack_base_IRQ boot_stack_len_IRQ BOOT_COLOR_IRQ
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BOOT_CHANGE_MODE BOOT_ARM_MODE_FIQ BOOT_ARM_MODE_MASK
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BOOT_SET_STACK boot_stack_base_FIQ boot_stack_len_FIQ BOOT_COLOR_FIQ
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//Clear FIQ banked registers while in FIQ mode
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MOV R8, #0
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MOV R9, #0
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MOV R10, #0
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MOV R11, #0
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MOV R12, #0
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BOOT_CHANGE_MODE BOOT_ARM_MODE_SVC BOOT_ARM_MODE_MASK
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BOOT_SET_STACK boot_stack_base_SVC boot_stack_len_SVC BOOT_COLOR_SVC
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/*Stay in Supervisor Mode, copy data from binary to ram*/
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BL _sysboot_copy_data_to_ram
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#if ((CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7271)) || (CONFIG_SOC_BK7236A)
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BL _sysboot_copy_code_to_itcm
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#endif
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#if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A)
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BL _sysboot_tcmbss_init
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#endif
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//Clear Registers
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MOV R0, #0
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MOV R1, #0
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MOV R2, #0
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MOV R3, #0
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MOV R4, #0
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MOV R5, #0
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MOV R6, #0
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MOV R7, #0
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MOV R8, #0
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MOV R9, #0
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MOV R10, #0
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MOV R11, #0
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MOV R12, #0
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/* start main entry*/
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B entry_main
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B .
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//Globals
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boot_stack_base_UNUSED:
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.word und_stack_start
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boot_stack_len_UNUSED:
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.word UND_STACK_SIZE
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boot_stack_base_IRQ:
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.word irq_stack_start
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boot_stack_len_IRQ:
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.word IRQ_STACK_SIZE
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boot_stack_base_SVC:
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.word svc_stack_start
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boot_stack_len_SVC:
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.word SVC_STACK_SIZE
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boot_stack_base_FIQ:
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.word fiq_stack_start
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boot_stack_len_FIQ:
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.word FIQ_STACK_SIZE
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boot_stack_base_SYS:
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.word sys_stack_start
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boot_stack_len_SYS:
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.word SYS_STACK_SIZE
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/*FUNCTION: _sysboot_copy_data_to_ram*/
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/*DESCRIPTION: copy main stack code from FLASH/ROM to SRAM*/
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_sysboot_copy_data_to_ram:
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LDR R0, =_data_flash_begin
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LDR R1, =_data_ram_begin
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LDR R2, =_data_ram_end
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4:
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CMP R1, R2
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LDRLO R4, [R0], #4
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STRLO R4, [R1], #4
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BLO 4b
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BX LR
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/*FUNCTION: _sysboot_zi_init*/
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/*DESCRIPTION: Initialise Zero-Init Data Segment*/
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_sysboot_zi_init:
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LDR R0, =_bss_start
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LDR R1, =_bss_end
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MOV R3, R1
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MOV R4, R0
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MOV R2, #0
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5:
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CMP R4, R3
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STRLO R2, [R4], #4
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BLO 5b
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BX LR
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#if ((CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7271)) || (CONFIG_SOC_BK7236A)
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/*FUNCTION: _sysboot_copy_code_to_itcm*/
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/*DESCRIPTION: copy itcm code from FLASH/ROM to SRAM*/
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_sysboot_copy_code_to_itcm:
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LDR R0, =_itcmcode_flash_begin
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LDR R1, =_itcmcode_ram_begin
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LDR R2, =_itcmcode_ram_end
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6:
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CMP R1, R2
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LDRLO R4, [R0], #4
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STRLO R4, [R1], #4
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BLO 6b
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BX LR
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#endif
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#if (CONFIG_SOC_BK7231N) || (CONFIG_SOC_BK7236A)
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/*FUNCTION: _sysboot_sdbss_init*/
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/*DESCRIPTION: Initialise Zero-Init Data Segment of TCM */
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_sysboot_tcmbss_init:
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LDR R0, =_tcmbss_start
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LDR R1, =_tcmbss_end
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MOV R3, R1
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MOV R4, R0
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MOV R2, #0
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8:
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CMP R4, R3
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STRLO R2, [R4], #4
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BLO 8b
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BX LR
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#endif
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.align 5
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do_undefined:
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LDMFD SP!, {R0-R1}
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PUSH_SVC_REG
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STMFD sp!,{r0-r1}
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PUSH_ALL_ARM_REG
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BOOT_CHANGE_MODE BOOT_ARM_MODE_UND BOOT_ARM_MODE_MASK
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LDMFD SP!, {R0-R1}
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B boot_exception_undefine
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.align 5
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do_pabort:
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LDMFD SP!, {R0-R1}
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PUSH_SVC_REG
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STMFD sp!,{r0-r1}
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PUSH_ALL_ARM_REG
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BOOT_CHANGE_MODE BOOT_ARM_MODE_ABT BOOT_ARM_MODE_MASK
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LDMFD SP!, {R0-R1}
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B boot_exception_prefetch_abort
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.align 5
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do_dabort:
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LDMFD SP!, {R0-R1}
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PUSH_SVC_REG
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STMFD sp!,{r0-r1}
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PUSH_ALL_ARM_REG
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BOOT_CHANGE_MODE BOOT_ARM_MODE_ABT BOOT_ARM_MODE_MASK
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LDMFD SP!, {R0-R1}
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B boot_exception_data_abort
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
do_reserved:
|
||
|
|
LDMFD SP!, {R0-R1}
|
||
|
|
PUSH_SVC_REG
|
||
|
|
B boot_exception_reserved
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
boot_undefined:
|
||
|
|
STMFD sp!,{r0-r1}
|
||
|
|
LDR R1, =0x40000c
|
||
|
|
LDR r0, [R1]
|
||
|
|
BX r0
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
boot_pabort:
|
||
|
|
STMFD sp!,{r0-r1}
|
||
|
|
LDR R1, =0x400010
|
||
|
|
LDR r0, [R1]
|
||
|
|
BX r0
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
boot_dabort:
|
||
|
|
STMFD sp!,{r0-r1}
|
||
|
|
LDR R1, =0x400014
|
||
|
|
LDR r0, [R1]
|
||
|
|
BX r0
|
||
|
|
|
||
|
|
.align 5
|
||
|
|
boot_reserved:
|
||
|
|
STMFD sp!,{r0-r1}
|
||
|
|
LDR R1, =0x400018
|
||
|
|
LDR r0, [R1]
|
||
|
|
BX r0
|
||
|
|
|
||
|
|
.code 32
|
||
|
|
.global arch_wait_for_interrupt
|
||
|
|
.type arch_wait_for_interrupt,%function
|
||
|
|
arch_wait_for_interrupt:
|
||
|
|
MOV R0, #0
|
||
|
|
MCR p15, 0, R0, c7, c0, 4
|
||
|
|
BX LR
|
||
|
|
|
||
|
|
.code 32
|
||
|
|
.globl arch_enable_align_fault
|
||
|
|
.type arch_enable_align_fault, %function
|
||
|
|
arch_enable_align_fault:
|
||
|
|
MRC p15, 0, R0, c1, c0, 0
|
||
|
|
ORR R0, R0, #0x02
|
||
|
|
MCR p15, 0, R0, c1, c0, 0
|
||
|
|
BX LR
|
||
|
|
|
||
|
|
.globl arch_disable_align_fault
|
||
|
|
.type arch_disable_align_fault, %function
|
||
|
|
arch_disable_align_fault:
|
||
|
|
MRC p15, 0, R0, c1, c0, 0
|
||
|
|
BIC R0, R0, #0x02
|
||
|
|
MCR p15, 0, R0, c1, c0, 0
|
||
|
|
BX LR
|