54 lines
1.7 KiB
C
54 lines
1.7 KiB
C
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// Copyright 2022-2023 Beken
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#include "sdkconfig.h"
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/* Important notice:
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*
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* Following macros are not public API, they are just for writing FPGA/Chip
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* debug code only.
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* */
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#define GPIO_UP(id) *(volatile uint32_t*) (SOC_AON_GPIO_REG_BASE + ((id) << 2)) = 2
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#define GPIO_DOWN(id) *(volatile uint32_t*) (SOC_AON_GPIO_REG_BASE + ((id) << 2)) = 0
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#define GPIO_UP_DOWN(id) do {\
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volatile uint32_t cnt;\
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for (int i = 0; i < 10; i++) {\
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if ((i % 2) == 0) GPIO_UP((id));\
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else GPIO_DOWN(id);\
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cnt = 1000;\
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while(--cnt > 0);\
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}\
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} while(0)
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#define REG_SET(r, l, h, v) do { \
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uint32_t reg_v = *(volatile uint32_t*)(r);\
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reg_v &= ~((( 1 << ((h) + 1)) - 1) & (~( (1 << (l)) - 1)));\
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reg_v |= ((v) << (l));\
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*(volatile uint32_t*)(r) = reg_v;\
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} while(0)
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#define REG_OR(r, l, h, v) do { \
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uint32_t reg_v = *(volatile uint32_t*)(r);\
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reg_v |= ((v) << (l));\
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*(volatile uint32_t*)(r) = reg_v;\
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} while(0)
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#define SYS_REG_SET(reg_id, l, h, v) REG_SET((SOC_SYSTEM_REG_BASE + ((reg_id) << 2)), (l), (h), (v))
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#define SYS_REG_OR(reg_id, l, h, v) REG_OR((SOC_SYSTEM_REG_BASE + ((reg_id) << 2)), (l), (h), (v))
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