507 lines
10 KiB
C
507 lines
10 KiB
C
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <common/bk_include.h>
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#include <driver/psram_types.h>
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#include "psram_hal.h"
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#include "psram_ll_macro_def.h"
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#include "bk_pm_internal_api.h"
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#include "sys_driver.h"
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#include "aon_pmu_ll.h"
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#include <driver/psram.h>
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#include <modules/chip_support.h>
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extern void delay_us(uint32_t us);
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static void psram_delay(volatile uint32_t times)
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{
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while(times--);
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}
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void psram_hal_set_sf_reset(uint32_t value)
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{
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psram_ll_set_sf_reset_value(value);
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}
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void psram_hal_set_cmd_reset(void)
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{
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psram_ll_set_reg8_value(0x4);
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}
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void psram_hal_cmd_write(uint32_t addr, uint32_t value)
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{
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psram_ll_set_write_address(addr);
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psram_ll_set_write_data(value);
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psram_ll_set_reg8_value(0x1);
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while(psram_ll_get_reg8_value() & 0x1);
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}
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uint32_t psram_hal_cmd_read(uint32_t addr)
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{
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uint8_t m = 10, i = 5;
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for (i = 5; i > 0; i--)
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{
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psram_ll_set_write_address(addr);
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psram_ll_set_reg8_value(0x2);
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m = 10;
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while(psram_ll_get_reg8_value() & 0x2)
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{
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for (int j = 0; j < 5000; j++) {}
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m--;
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if (m == 0)
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break;
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};
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if (m != 0)
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{
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return psram_ll_get_regb_value();
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}
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psram_hal_set_sf_reset(0);
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psram_hal_set_sf_reset(1);
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psram_hal_set_cmd_reset();
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}
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return 0;
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}
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void psram_hal_set_clk(psram_clk_t clk)
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{
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switch (clk)
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{
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case PSRAM_240M:
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sys_drv_psram_clk_sel(1); // clk sel: 0-320 1-480
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sys_drv_psram_set_clkdiv(0); //frq: F/(2 + (1+div))
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break;
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case PSRAM_160M:
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sys_drv_psram_clk_sel(0); // clk sel: 0-320 1-480
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sys_drv_psram_set_clkdiv(0); //frq: F/(2 + (1+div))
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break;
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case PSRAM_120M:
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sys_drv_psram_clk_sel(1); // clk sel: 0-320 1-480
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sys_drv_psram_set_clkdiv(1); //frq: F/(2 + (1+div))
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break;
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case PSRAM_80M:
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sys_drv_psram_clk_sel(0); // clk sel: 0-320 1-480
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sys_drv_psram_set_clkdiv(1); //frq: F/(2 + (1+div))
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break;
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default:
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break;
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}
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}
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void psram_hal_set_voltage(psram_voltage_t voltage)
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{
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#if (COINFG_SOC_BK7256XX)
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switch (voltage)
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{
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case PSRAM_OUT_3_20V:
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sys_drv_psram_psldo_vset(0, 1);
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break;
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case PSRAM_OUT_3_0V:
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sys_drv_psram_psldo_vset(0, 0);
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break;
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case PSRAM_OUT_2_0V:
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sys_drv_psram_psldo_vset(1, 1);
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break;
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case PSRAM_OUT_1_80V:
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sys_drv_psram_psldo_vset(1, 0);
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break;
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default:
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break;
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}
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#else
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switch (voltage)
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{
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case PSRAM_OUT_3_0V:
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sys_drv_psram_psldo_vset(0, 0);
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break;
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case PSRAM_OUT_1_95V:
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sys_drv_psram_psldo_vset(1, 0);
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break;
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case PSRAM_OUT_1_90V:
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sys_drv_psram_psldo_vset(1, 1);
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break;
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case PSRAM_OUT_1_85V:
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sys_drv_psram_psldo_vset(1, 2);
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break;
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case PSRAM_OUT_1_80V:
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sys_drv_psram_psldo_vset(1, 3);
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break;
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default:
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break;
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}
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#endif
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}
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static inline bool is_psram_addr_out_of_range(uint32_t addr)
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{
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#if (CONFIG_PSRAM_WRITE_THROUGH)
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return ((addr < SOC_PSRAM_DATA_BASE) || (addr > (SOC_PSRAM_DATA_BASE + SOC_PSRAM_DATA_SIZE)));
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#else
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return false;
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#endif
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}
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static inline bool is_32bytes_aligned(uint32_t addr)
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{
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return ((addr & 0x1f) == 0);
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}
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int psram_hal_set_write_through(psram_write_through_area_t area, uint32_t enable, uint32_t start, uint32_t end)
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{
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#if (CONFIG_PSRAM_WRITE_THROUGH)
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if (area > PSRAM_WRITE_THROUGH_AREA_COUNT) {
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return BK_ERR_PSRAM_AREA;
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}
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if (enable) {
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if (start >= end) {
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return BK_ERR_PSRAM_ADDR_RELATION;
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}
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if (is_psram_addr_out_of_range(start) || is_psram_addr_out_of_range(end)) {
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return BK_ERR_PSRAM_ADDR_OUT_OF_RANGE;
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}
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if ((!is_32bytes_aligned(start)) || (!is_32bytes_aligned(end))) {
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return BK_ERR_PSRAM_ADDR_ALIGN;
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}
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psram_ll_set_cover_start(area, start >> 5);
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psram_ll_set_cover_stop_enable(area, BIT(31) | (end >> 5));
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} else {
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psram_ll_set_cover_stop_enable(area, 0);
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}
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return BK_OK;
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#else
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return BK_FAIL;
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#endif
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}
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void psram_hal_set_transfer_mode(uint32_t value)
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{
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psram_ll_set_reg4_wrap_config(value);
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}
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static int psram_hal_APS6408L_init(uint32_t *id)
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{
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uint32_t val = 0;
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#if (CONFIG_SOC_BK7256XX)
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uint32_t chip_id = bk_get_hardware_chip_id_version();
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if (chip_id == CHIP_VERSION_C)
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psram_hal_set_mode_value(PSRAM_MODE1);
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else
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psram_hal_set_mode_value(PSRAM_MODE3);
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#else
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psram_hal_set_mode_value(PSRAM_MODE6);//PSRAM_MODE2
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//psram_hal_set_reg5_value(0x282);
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psram_hal_set_reg5_value(0x380);
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#endif
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psram_hal_set_cmd_reset();
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psram_delay(500);
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val = psram_hal_cmd_read(0x00000000);//1 0001 10001101
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#if (CONFIG_SOC_BK7256XX)
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// 8 line
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val = ((val >> 8) & 0xFF) | ((val & 0xFF) << 8);
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#endif
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if (val == 0 || val != *id)
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{
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return -1;
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}
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else
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{
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*id = val;
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}
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val = psram_hal_get_regb_value();
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#if (CONFIG_SOC_BK7256XX)
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val = (val & ~(0x1F << 8)) | (0x4 << 10) | (0x3 << 8);
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#else
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val = (val & ~(0x1F)) | (0x4 << 2) | 0x3;
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#endif
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psram_hal_cmd_write(0x00000000, val);
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psram_hal_cmd_read(0x00000000);//1 0001 10001101
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psram_hal_cmd_read(0x00000004);
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val = psram_hal_get_regb_value();
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#if (CONFIG_SOC_BK7256XX)
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val = (val & ~(0x7 << 13)) | (0x6 << 13);//write latency 110 166Mhz
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#else
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val = (val & ~(0x7 << 5)) | (0x6 << 5);
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#endif
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psram_hal_cmd_write(0x00000004, val);
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return 0;
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}
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static int psram_hal_W955D8MKY_5J_init(uint32_t *id)
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{
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uint32_t val = 0;
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uint32_t io_drv = 0; /*range [0, 3]*/
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#if (CONFIG_SOC_BK7256XX)
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psram_hal_set_mode_value(PSRAM_MODE4);// mode 4
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#elif (CONFIG_SOC_BK7236XX)
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psram_hal_set_mode_value(PSRAM_MODE8);// mode 8
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#endif
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#if (!CONFIG_SOC_BK7256XX)
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psram_hal_set_reg5_value(0x292);
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//psram_hal_set_reg5_value(0x380); //NOTES:APS PSRAM drive stength needs changed.This type PSRAM needs to be verified.
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#endif
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psram_hal_set_cmd_reset();
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psram_delay(500);
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val = psram_hal_cmd_read(0x01000000);
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(VOID *)val;
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#if (CONFIG_SOC_BK7256XX)
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// 8 line
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val = ((val >> 8) & 0xFF) | ((val & 0xFF) << 8);
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#endif
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#if (CONFIG_SOC_BK7256XX)
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val = 0x8F1C | (io_drv << 12);
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#else
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val = 0x1C8F | (io_drv << 4);
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#endif
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#if (CONFIG_SOC_BK7256XX)
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psram_hal_cmd_write(0x01000000, val);
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#elif (CONFIG_SOC_BK7236XX)
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psram_hal_cmd_write(0x01000000, 0x1c8f);
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#endif
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psram_hal_cmd_read(0x01000000);
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return 0;
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}
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static int psram_hal_APS128XXO_OB9_init(uint32_t *id)
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{
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uint32_t val = 0;
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psram_hal_set_mode_value(PSRAM_MODE7);
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#if (!CONFIG_SOC_BK7256XX)
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//psram_hal_set_reg5_value(0x292);
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psram_hal_set_reg5_value(0x380);
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#endif
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psram_hal_set_cmd_reset();
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psram_delay(500);
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val = psram_hal_cmd_read(0x00000000);//1 0001 10001101
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#if (CONFIG_SOC_BK7256XX)
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// 8 line
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val = ((val >> 8) & 0xFF) | ((val & 0xFF) << 8);
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#endif
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if (val == 0 || val != *id)
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{
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return -1;
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}
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else
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{
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*id = val;
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}
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val = psram_hal_get_regb_value();
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#if (CONFIG_SOC_BK7256XX)
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val = (val & ~(0x7 << 10)) | (0x4 << 10);
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#else
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val = (val & ~(0x7 << 2)) | (0x4 << 2);
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#endif
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psram_hal_cmd_write(0x00000000, val);
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psram_hal_cmd_read(0x00000004);
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val = psram_hal_get_regb_value();
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#if (CONFIG_SOC_BK7256XX)
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val = (val & ~(0x7 << 13)) | (0x6 << 13);
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#else
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val = (val & ~(0x7 << 5)) | (0x6 << 5);
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#endif
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psram_hal_cmd_write(0x00000004, val);
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psram_hal_cmd_read(0x00000008);//1 0001 10001101
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val = psram_hal_get_regb_value();
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val |= 0x40;
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psram_hal_cmd_write(0x00000008,val);
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return 0;
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}
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uint32_t psram_hal_config_init(uint32_t id)
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{
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int ret = 0;
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uint32_t val = 0;
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uint32_t type = id;
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psram_hal_set_sf_reset(1);
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/* set psram bypass */
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val = psram_hal_get_reg2_value();
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val |= (0x1 << 1);
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psram_hal_set_reg2_value(val);
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if (id != 0)
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{
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if (id == PSRAM_APS6408L_ID)
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{
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psram_hal_APS6408L_init(&type);
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return type;
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||
|
|
}
|
||
|
|
else if (id == PSRAM_APS128XXO_OB9_ID)
|
||
|
|
{
|
||
|
|
psram_hal_APS128XXO_OB9_init(&type);
|
||
|
|
return type;
|
||
|
|
}
|
||
|
|
else //id == PSRAM_W955D8MKY_5J_ID
|
||
|
|
{
|
||
|
|
psram_hal_W955D8MKY_5J_init(&type);
|
||
|
|
return type;
|
||
|
|
}
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
type = PSRAM_APS6408L_ID;
|
||
|
|
ret = psram_hal_APS6408L_init(&type);
|
||
|
|
if (ret == 0)
|
||
|
|
{
|
||
|
|
return type;
|
||
|
|
}
|
||
|
|
|
||
|
|
type = PSRAM_APS128XXO_OB9_ID;
|
||
|
|
ret = psram_hal_APS128XXO_OB9_init(&type);
|
||
|
|
if (ret == 0)
|
||
|
|
{
|
||
|
|
return type;
|
||
|
|
}
|
||
|
|
|
||
|
|
type = PSRAM_W955D8MKY_5J_ID;
|
||
|
|
ret = psram_hal_W955D8MKY_5J_init(&type);
|
||
|
|
|
||
|
|
return type;
|
||
|
|
}
|
||
|
|
|
||
|
|
}
|
||
|
|
|
||
|
|
// config 1: psram power and clk config, need wait clk stable
|
||
|
|
void psram_hal_power_clk_enable(uint8_t enable)
|
||
|
|
{
|
||
|
|
if (enable)
|
||
|
|
{
|
||
|
|
psram_delay(500);
|
||
|
|
|
||
|
|
sys_drv_psram_ldo_enable(1);
|
||
|
|
delay_us(1000);
|
||
|
|
|
||
|
|
bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_AHBP_PSRAM, PM_POWER_MODULE_STATE_ON);
|
||
|
|
|
||
|
|
// psram bus clk always open
|
||
|
|
sys_drv_psram_psram_disckg(1);
|
||
|
|
|
||
|
|
//psram 80M
|
||
|
|
psram_hal_set_clk(PSRAM_80M);
|
||
|
|
|
||
|
|
sys_drv_dev_clk_pwr_up(CLK_PWR_ID_PSRAM, CLK_PWR_CTRL_PWR_UP);//psram_clk_enable bit19=1
|
||
|
|
}
|
||
|
|
else
|
||
|
|
{
|
||
|
|
bk_psram_heap_init_flag_set(false);
|
||
|
|
|
||
|
|
bk_pm_module_vote_power_ctrl(PM_POWER_SUB_MODULE_NAME_AHBP_PSRAM, PM_POWER_MODULE_STATE_OFF);
|
||
|
|
psram_hal_set_sf_reset(0);
|
||
|
|
|
||
|
|
sys_drv_dev_clk_pwr_up(CLK_PWR_ID_PSRAM, CLK_PWR_CTRL_PWR_DOWN);//psram_clk_disable
|
||
|
|
|
||
|
|
// power down
|
||
|
|
sys_drv_psram_ldo_enable(0);
|
||
|
|
}
|
||
|
|
|
||
|
|
psram_delay(3000);
|
||
|
|
}
|
||
|
|
|
||
|
|
// config 2: reset psram and wait psram ready
|
||
|
|
void psram_hal_reset(void)
|
||
|
|
{
|
||
|
|
#if (CONFIG_SOC_BK7256XX)
|
||
|
|
psram_hal_set_sf_reset(1);
|
||
|
|
|
||
|
|
#if (CONFIG_PSRAM_APS6408L_O)
|
||
|
|
|
||
|
|
int chip_id = bk_get_hardware_chip_id_version();
|
||
|
|
|
||
|
|
if (chip_id == CHIP_VERSION_C)
|
||
|
|
psram_hal_set_mode_value(PSRAM_MODE1);
|
||
|
|
else
|
||
|
|
psram_hal_set_mode_value(PSRAM_MODE3);
|
||
|
|
#else
|
||
|
|
//psram_hal_set_mode_value(PSRAM_MODE5);// mode 5
|
||
|
|
psram_hal_set_mode_value(PSRAM_MODE4);// mode 4
|
||
|
|
#endif
|
||
|
|
psram_hal_set_cmd_reset();
|
||
|
|
#endif //CONFIG_SOC_BK7256XX
|
||
|
|
}
|
||
|
|
|
||
|
|
// config 3: psram config
|
||
|
|
void psram_hal_config(void)
|
||
|
|
{
|
||
|
|
#if (CONFIG_SOC_BK7256XX)
|
||
|
|
uint32_t val = 0;
|
||
|
|
|
||
|
|
#if (CONFIG_PSRAM_APS6408L_O)
|
||
|
|
|
||
|
|
psram_hal_cmd_read(0x00000000);//1 0001 10001101
|
||
|
|
|
||
|
|
val = psram_hal_get_regb_value();
|
||
|
|
|
||
|
|
val = (val & ~(0x1F << 8)) | (0x4 << 10) | (0x3 << 8);
|
||
|
|
|
||
|
|
psram_hal_cmd_write(0x00000000, val);
|
||
|
|
|
||
|
|
psram_hal_cmd_read(0x00000000);//1 0001 10001101
|
||
|
|
|
||
|
|
psram_hal_cmd_read(0x00000004);
|
||
|
|
|
||
|
|
val = psram_hal_get_regb_value();
|
||
|
|
val = (val & ~(0x7 << 13)) | (0x6 << 13);//write latency 110 166Mhz
|
||
|
|
|
||
|
|
psram_hal_cmd_write(0x00000004, val);
|
||
|
|
#else
|
||
|
|
uint32_t io_drv = 0; /*range [0, 3]*/
|
||
|
|
|
||
|
|
val = psram_hal_cmd_read(0x01000000);
|
||
|
|
|
||
|
|
//val = 0x8F1F | (io_drv << 12);// mode 5
|
||
|
|
val = 0x8F1C | (io_drv << 12);// mode 4
|
||
|
|
|
||
|
|
psram_hal_cmd_write(0x01000000, val);
|
||
|
|
|
||
|
|
psram_hal_cmd_read(0x01000000);
|
||
|
|
#endif
|
||
|
|
|
||
|
|
#endif //CONFIG_SOC_BK7256XX
|
||
|
|
}
|
||
|
|
|
||
|
|
|